Analog Devices ADP5023 Evaluation Board ADP5023CP-EVALZ ADP5023CP-EVALZ Data Sheet
Product codes
ADP5023CP-EVALZ
Dual 3 MHz, 800 mA Buck
Regulators with One 300 mA LDO
Data Sheet
Rev. D
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FEATURES
Main input voltage range: 2.3 V to 5.5 V
Two 800 mA buck regulators and one 300 mA LDO
24-lead, 4 mm × 4 mm LFCSP package
Regulator accuracy: ±1.8%
Factory programmable or external adjustable VOUTx
3 MHz buck operation with forced PWM and auto PWM/PSM
Two 800 mA buck regulators and one 300 mA LDO
24-lead, 4 mm × 4 mm LFCSP package
Regulator accuracy: ±1.8%
Factory programmable or external adjustable VOUTx
3 MHz buck operation with forced PWM and auto PWM/PSM
modes
BUCK1/BUCK2: output voltage range from 0.8 V to 3.8 V
LDO: output voltage range from 0.8 V to 5.2 V
LDO: input supply voltage from 1.7 V to 5.5 V
LDO: high PSRR and low output noise
LDO: output voltage range from 0.8 V to 5.2 V
LDO: input supply voltage from 1.7 V to 5.5 V
LDO: high PSRR and low output noise
APPLICATIONS
Power for processors, ASIC, FPGAs, and RF chipsets
Portable instrumentation and medical devices
Space constrained devices
Portable instrumentation and medical devices
Space constrained devices
GENERAL DESCRIPTION
combines two high performance buck regulators
and one low dropout (LDO) regulator in a small, 24-lead 4 mm ×
4 mm LFCSP to meet demanding performance and board space
requirements.
The high switching frequency of the buck regulators enables tiny
multilayer external components and minimizes the board space.
When the MODE pin is set high, the buck regulators operate in
forced PWM mode. When the MODE pin is set low, the buck
regulators operate in PWM mode when the load current is
4 mm LFCSP to meet demanding performance and board space
requirements.
The high switching frequency of the buck regulators enables tiny
multilayer external components and minimizes the board space.
When the MODE pin is set high, the buck regulators operate in
forced PWM mode. When the MODE pin is set low, the buck
regulators operate in PWM mode when the load current is
above a predefined threshold. When the load current falls below
a predefined threshold, the regulator operates in power save
mode (PSM) improving the light-load efficiency.
a predefined threshold, the regulator operates in power save
mode (PSM) improving the light-load efficiency.
Table 1. Family Models
Model
Channels
Maximum
Current
Current
Package
2 buck, 1 LDO
800 mA,
300 mA
300 mA
LFCSP (CP-24-10)
2 buck, 1 LDO
1.2 A, 300 mA
LFCSP (CP-24-10)
2 buck, 2 LDOs
1.2 A, 300 mA
LFCSP (CP-24-10),
TSSOP (RE-28-1)
2 buck, 2 LDOs
800 mA,
300 mA
300 mA
LFCSP (CP-24-10)
2 buck, 2 LDOs
with 2 EN pins
800 mA,
300 mA
WLCSP (CB-16-8)
1 buck, 2 LDOs
1.2 A, 300 mA
LFCSP (CP-20-10)
1 buck, 2 LDOs with
supervisory, watch-
supervisory, watch-
dog, manual reset
1.2 A, 300 mA
LFCSP (CP-20-10)
The two bucks operate out of phase to reduce the input capaci-
tor requirement. The low quiescent current, low dropout voltage,
and wide input voltage range of the
tor requirement. The low quiescent current, low dropout voltage,
and wide input voltage range of the
LDO extends the
battery life of portable devices. The
LDO maintains
power supply rejection greater than 60 dB for frequencies as
high as 10 kHz while operating with a low headroom voltage.
Regulators in the
high as 10 kHz while operating with a low headroom voltage.
Regulators in the
are activated though dedicated
enable pins. The default output voltages can be externally set in
the adjustable version or factory programmable to a wide range
of preset values in the fixed voltage version.
the adjustable version or factory programmable to a wide range
of preset values in the fixed voltage version.
TYPICAL APPLICATION CIRCUIT
VIN1
VIN3
EN1
PWM
PSM/PWM
2.3V TO
5.5V
SW1
FB1
R2
R1
VOUT1
PGND1
MODE
C5
10µF
10µF
V
OUT1
AT
800mA
V
OUT2
AT
800mA
V
OUT3
AT
300mA
L1 1µH
EN1
BUCK1
MODE
C3
1µF
C2
4.7µF
C1
4.7µF
AVIN
C
FILT
0.1µF
VIN2
EN2
AGND
EN2
BUCK2
MODE
EN3
1.7V TO
5.5V
ON
OFF
ON
OFF
EN3
LDO
ADP5023
HOUSEKEEPING
SW2
FB2
R4
R3
VOUT2
PGND2
C6
10µF
10µF
L2 1µH
FB3
R6
R5
VOUT3
C7
1µF
1µF
09889-
001
Figure 1.