Analog Devices AD5445 Evaluation Board EVAL-AD5445SDZ EVAL-AD5445SDZ Data Sheet
Product codes
EVAL-AD5445SDZ
AD5424/AD5433/AD5445
Data Sheet
Rev. D | Page 24 of 28
PCB LAYOUT AND POWER SUPPLY DECOUPLING
In any circuit where accuracy is important, careful consideration of
the power supply and ground return layout helps to ensure the
rated performance. The printed circuit board on which the
the power supply and ground return layout helps to ensure the
rated performance. The printed circuit board on which the
that the analog and digital sections are separated and confined
to certain areas of the board. If the DAC is in a system where
multiple devices require an AGND-to-DGND connection, the
connection should be made at one point only. The star ground
point should be established as close as possible to the device.
These DACs should have ample supply bypassing of 10 µF in
parallel with 0.1 µF on the supply, located as close to the package
as possible and ideally right up against the device. The 0.1 µF
capacitor should have low effective series resistance (ESR) and
effective series inductance (ESI), like the common ceramic types
that provide a low impedance path to ground at high frequencies,
to handle transient currents due to internal logic switching. Low
ESR 1 µF to 10 µF tantalum or electrolytic capacitors should also be
applied at the supplies to minimize transient disturbance and filter
out low frequency ripple.
to certain areas of the board. If the DAC is in a system where
multiple devices require an AGND-to-DGND connection, the
connection should be made at one point only. The star ground
point should be established as close as possible to the device.
These DACs should have ample supply bypassing of 10 µF in
parallel with 0.1 µF on the supply, located as close to the package
as possible and ideally right up against the device. The 0.1 µF
capacitor should have low effective series resistance (ESR) and
effective series inductance (ESI), like the common ceramic types
that provide a low impedance path to ground at high frequencies,
to handle transient currents due to internal logic switching. Low
ESR 1 µF to 10 µF tantalum or electrolytic capacitors should also be
applied at the supplies to minimize transient disturbance and filter
out low frequency ripple.
Fast switching signals such as clocks should be shielded with
digital ground to avoid radiating noise to other parts of the
board and should never be run near the reference inputs.
Avoid crossover of digital and analog signals. Traces on opposite
sides of the board should run at right angles to each other. This
reduces the effects of feedthrough through the board. A micro-
strip technique is by far the best, but not always possible with a
double-sided board. In this technique, the component side of
the board is dedicated to the ground plane, while signal traces
are placed on the solder side.
It is good practice to employ compact, minimum lead length
PCB layout design. Leads to the input should be as short as
possible to minimize IR drops and stray inductance.
The PCB metal traces between V
digital ground to avoid radiating noise to other parts of the
board and should never be run near the reference inputs.
Avoid crossover of digital and analog signals. Traces on opposite
sides of the board should run at right angles to each other. This
reduces the effects of feedthrough through the board. A micro-
strip technique is by far the best, but not always possible with a
double-sided board. In this technique, the component side of
the board is dedicated to the ground plane, while signal traces
are placed on the solder side.
It is good practice to employ compact, minimum lead length
PCB layout design. Leads to the input should be as short as
possible to minimize IR drops and stray inductance.
The PCB metal traces between V
REF
and R
FB
should also be
matched to minimize gain error. To maximize high frequency
performance, the I-to-V amplifier should be located as close to
the device as possible.
performance, the I-to-V amplifier should be located as close to
the device as possible.
Table 12. Overview of AD54xx and AD55xx Devices
Part No.
Resolution
No. DACs
INL(LSB)
Interface
Package
Features
8
1
±0.25
Parallel
RU-16, CP-20
10 MHz BW, 17 ns CS pulse width
8
1
±0.25
Serial
RM-10
10 MHz BW, 50 MHz serial
8
2
±0.25
Parallel
RU-20
10 MHz BW, 17 ns CS pulse width
8
2
±0.25
Serial
RU-10
10 MHz BW, 50 MHz serial
8
1
±0.25
Serial
RJ-8
10 MHz BW, 50 MHz serial
10
1
±0.5
Serial
RM-10
10 MHz BW, 50 MHz serial
10
1
±0.5
Parallel
RU-20, CP-20
10 MHz BW, 17 ns CS pulse width
10
2
±0.5
Serial
RU-16
10 MHz BW, 50 MHz serial
10
2
±0.5
Parallel
RU-24
10 MHz BW, 17 ns CS pulse width
10
1
±0.25
Serial
RJ-8
10 MHz BW, 50 MHz serial
12
1
±1
Serial
RM-10
10 MHz BW, 50 MHz serial
12
1
±0.5
Serial
RM-8
50 MHz serial interface
12
2
±1
Serial
RU-24
10 MHz BW, 50 MHz serial
12
2
±1
Parallel
CP-40
10 MHz BW, 17 ns CS pulse width
12
2
±1
Parallel
RU-20, CP-20
10 MHz BW, 17 ns CS pulse width
12
2
±1
Parallel
RU-24
10 MHz BW, 17 ns CS pulse width
12
2
±1
Serial
RU-16
10 MHz BW, 50 MHz serial
12
1
±0.5
Serial
RJ-8, RM-8
10 MHz BW, 50 MHz serial
14
1
±1
Serial
RM-8
10 MHz BW, 50 MHz serial
14
1
±2
Serial
UJ-8, RM-8
10 MHz BW, 50 MHz serial
14
1
±1
Serial
RM-8
4 MHz BW, 50 MHz serial clock
14
1
±1
Parallel
RU-28
4 MHz BW, 20 ns WR pulse width
14
2
±1
Serial
RM-8
4 MHz BW, 50 MHz serial clock
14
2
±1
Parallel
RU-38
4 MHz BW, 20 ns WR pulse width
16
1
±2
Serial
RM-8
4 MHz BW, 50 MHz serial clock
16
1
±2
Parallel
RU-28
4 MHz BW, 20 ns WR pulse width
16
2
±2
Serial
RU-16
4 MHz BW, 50 MHz serial clock
16
2
±2
Parallel
RU-38
4 MHz BW, 20 ns WR pulse width