Analog Devices AD9648 Evaluation Board AD9648-125EBZ AD9648-125EBZ Data Sheet
Product codes
AD9648-125EBZ
14-Bit, 125 MSPS/105 MSPS, 1.8 V Dual
Analog-to-Digital Converter
Rev.
0
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Tel: 781.329.4700
Fax: 781.461.3113
©
2011 Analog Devices, Inc. All rights reserved.
FEATURES
1.8 V analog supply operation
1.8 V CMOS or LVDS outputs
SNR = 74.5 dBFS @ 70 MHz
SFDR = 91 dBc @ 70 MHz
Low power: 78 mW/channel ADC core @ 125 MSPS
Differential analog input with 650 MHz bandwidth
IF sampling frequencies to 200 MHz
On-chip voltage reference and sample-and-hold circuit
2 V p-p differential analog input
DNL = ±0.35 LSB
Serial port control options
1.8 V CMOS or LVDS outputs
SNR = 74.5 dBFS @ 70 MHz
SFDR = 91 dBc @ 70 MHz
Low power: 78 mW/channel ADC core @ 125 MSPS
Differential analog input with 650 MHz bandwidth
IF sampling frequencies to 200 MHz
On-chip voltage reference and sample-and-hold circuit
2 V p-p differential analog input
DNL = ±0.35 LSB
Serial port control options
Offset binary, gray code, or twos complement data format
Optional clock duty cycle stabilizer
Integer 1-to-8 input clock divider
Data output multiplex option
Built-in selectable digital test pattern generation
Energy-saving power-down modes
Data clock out with programmable clock and data
Optional clock duty cycle stabilizer
Integer 1-to-8 input clock divider
Data output multiplex option
Built-in selectable digital test pattern generation
Energy-saving power-down modes
Data clock out with programmable clock and data
alignment
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers
Diversity radio systems
Multimode digital receivers
GSM, EDGE, W-CDMA, LTE,
CDMA2000, WiMAX, TD-SCDMA
CDMA2000, WiMAX, TD-SCDMA
I/Q demodulation systems
Smart antenna systems
Broadband data applications
Battery-powered instruments
Hand held scope meters
Portable medical imaging
Ultrasound
Radar/LIDAR
Smart antenna systems
Broadband data applications
Battery-powered instruments
Hand held scope meters
Portable medical imaging
Ultrasound
Radar/LIDAR
1
This product is protected by a U.S patent.
FUNCTIONAL BLOCK DIAGRAM
VIN+A
VIN–A
VREF
SENSE
VCM
RBIAS
VIN–B
VIN+B
ORA
D0A
D13A
DCOA
DRVDD
ORB
D13B
D0B
DCOB
SDIO
AGND
AVDD
SCLK
SPI
PROGRAMMING DATA
M
U
X
OP
TION
PDWN DFS
CLK+ CLK–
MODE
CONTROLS
DCS
DUTY CYCLE
STABILIZER
SYNC
DIVIDE
1 TO 8
OEB
CSB
REF
SELECT
ADC
C
MO
S/
L
V
DS
OU
TP
U
T B
U
FFE
R
ADC
C
MO
S/
L
V
DS
OU
TP
U
T B
U
FFE
R
AD9648
09975-
001
NOTES
1. PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY;
SEE FIGURE 7 FOR LVDS PIN NAMES.
1. PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY;
SEE FIGURE 7 FOR LVDS PIN NAMES.
Figure 1.
PRODUCT HIGHLIGHTS
operates from a single 1.8 V analog
power supply and features a separate digital output
driver supply to accommodate 1.8 V CMOS or LVDS
logic families.
driver supply to accommodate 1.8 V CMOS or LVDS
logic families.
2. The patented sample-and-hold circuit maintains
excellent performance for input frequencies up to
200 MHz and is designed for low cost, low power, and
ease of use.
200 MHz and is designed for low cost, low power, and
ease of use.
3. A standard serial port interface supports various
product features and functions, such as data output
formatting, internal clock divider, power-down,
DCO/data timing and offset adjustments.
formatting, internal clock divider, power-down,
DCO/data timing and offset adjustments.
14-bit
ADC, the
12-bit ADCs, and the
AD9608/
10-bit ADCs, enabling a simple
migration path between 10-bit and 16-bit converters
sampling from 20 MSPS to 125 MSPS.
sampling from 20 MSPS to 125 MSPS.