Atmel MCU Evaluation Kit AT91SAM7X-EK AT91SAM7X-EK Data Sheet

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SAM7X Series [SUMMARY DATASHEET]

6120IS–ATARM–14-Nov-13

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Embedded Flash Controller



Embedded Flash interface, up to three programmable wait states

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Prefetch buffer, buffering and anticipating the 16-bit requests, reducing the required wait states

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Key-protected program, erase and lock/unlock sequencer

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Single command for erasing, programming and locking operations

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Interrupt generation in case of forbidden operation

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Handles data transfer between peripherals and memories

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Thirteen channels



Two for each USART

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Two for the Debug Unit

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Two for the Serial Synchronous Controller



Two for each Serial Peripheral Interface

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One for the Analog-to-digital Converter

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Low bus arbitration overhead

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One Master Clock cycle needed for a transfer from memory to peripheral



Two Master Clock cycles needed for a transfer from peripheral to memory



Next Pointer management for reducing interrupt latency requirements

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Peripheral DMA Controller (PDC) priority is as follows (from the highest priority to the lowest):

 

Receive DBGU 

Receive USART0

Receive USART1

Receive SSC

Receive ADC

Receive SPI0

Receive SPI1

Transmit

DBGU

Transmit

USART0

Transmit

USART

Transmit

SSC

Transmit

SPI0

Transmit

SPI1