Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Data Sheet
Product codes
AT91SAM9M10-G45-EK
Connectors
AT91SAM9M10-G45-EK User Guide
6-5
6495B–ATARM–21-Apr-10
Table 6-7. JTAG/ICE Connector J13 Signal Descriptions
Pin
Mnemonic
Description
1
VTref. 3.3V power
This is the target reference voltage. It is used to check if the target
has power, to create the logic-level reference for the input
comparators, and to control the output logic levels to the target. It is
normally fed from VDD on the target board and must not have a
series resistor.
has power, to create the logic-level reference for the input
comparators, and to control the output logic levels to the target. It is
normally fed from VDD on the target board and must not have a
series resistor.
2
Vsupply. 3.3V power
This pin is not connected in SAM-ICE. It is reserved for compatibility
with other equipment. Connect to VDD or leave open in target
system.
with other equipment. Connect to VDD or leave open in target
system.
3
nTRST TARGET RESET - Active-low output
signal that resets the target
signal that resets the target
JTAG Reset. Output from SAM-ICE to the Reset signal on the target
JTAG port. Typically connected to nTRST on the target CPU. This pin
is normally pulled HIGH on the target to avoid unintentional resets
when there is no connection.
JTAG port. Typically connected to nTRST on the target CPU. This pin
is normally pulled HIGH on the target to avoid unintentional resets
when there is no connection.
4
GND
Common ground
5
TDI TEST DATA INPUT - Serial data output line,
sampled on the rising edge of the TCK signal.
sampled on the rising edge of the TCK signal.
JTAG data input of target CPU. It is recommended that this pin is
pulled to a defined state on the target board. Typically connected to
TDI on target CPU.
pulled to a defined state on the target board. Typically connected to
TDI on target CPU.
6
GND
Common ground
7
TMS TEST MODE SELECT
JTAG mode set input of target CPU. This pin should be pulled up on
the target. Typically connected to TMS on target CPU. Output signal
that sequences the target's JTAG state machine, sampled on the
rising edge of the TCK signal.
the target. Typically connected to TMS on target CPU. Output signal
that sequences the target's JTAG state machine, sampled on the
rising edge of the TCK signal.
8
GND Common
ground
9
TCK TEST CLOCK - Output timing signal, for
synchronizing test logic and control register
access.
synchronizing test logic and control register
access.
JTAG clock signal to target CPU. It is recommended that this pin is
pulled to a defined state on the target board. Typically connected to
TCK on target CPU.
pulled to a defined state on the target board. Typically connected to
TCK on target CPU.
10
GND
Common ground
11
RTCK - Input Return test clock signal from the
target.
target.
Some targets must synchronize the JTAG inputs to internal clocks. To
assist in meeting this requirement, a returned and retimed TCK can
be used to dynamically control the TCK rate. SAM-ICE supports
adaptive clocking which waits for TCK changes to be echoed
correctly before making further changes. Connect to RTCK if
available, otherwise to GND
assist in meeting this requirement, a returned and retimed TCK can
be used to dynamically control the TCK rate. SAM-ICE supports
adaptive clocking which waits for TCK changes to be echoed
correctly before making further changes. Connect to RTCK if
available, otherwise to GND
12
GND
Common ground
13
TDO JTAG TEST DATA OUTPUT - Serial data
input from the target.
input from the target.
JTAG data output from target CPU. Typically connected to TDO on
target CPU.
target CPU.
14
GND
Common ground
15
nSRST RESET
Active-low reset signal. Target CPU reset signal
16
GND
Common ground
17
RFU
This pin is not connected in SAM-ICE.
18
GND
Common ground
19
RFU
This pin is not connected in SAM-ICE
20
GND
Common ground