Atmel Xplained Evaluation Board AT32UC3L0-XPLD AT32UC3L0-XPLD Data Sheet

32099G–06/2011

Please note that the referring page numbers in this section are referred to this document. The
referring revision in this section are referring to the document revision.

1.

FLASHCDW: FSR register is a Read-only register. Added info about QPRUP

2.

PM: Clarified POR33 masking requirements before shutdown. Added more info about wakeup 
sources. Added AWEN description. PPCR register reset value corrected.

3.

SAU: SR.IDLE definition and reset value corrected.

4.

DFLL: Open- and closed-loop operation clarified. 

5.

OSC32: Added note about OSC32RDY bit not always cleared when disabling OSC32.

6.

USART: Major cleanup.

1.

Features: Removed superfluous R mark.

2.

Package and Pinout, GPIO function multiplexing:TWIMS0-TWCK on PA20 removed. ADCIFB-
AD[3] on PA17 removed, number of ADC channels are 8, not 9. These were removed from rev. 
C, but reappeared in rev. E.

1.

Overview: Added missing signals in block diagram.

2.

Package and pinout: Added note about TWI, SMBUS and 5V tolerant pads in peripheral 
multiplexing. Added CAT DIS signal to signal descriptions. Removed TBD on ADVREFP 
minimum voltage.

3.

Memories: Added SAU slave address to physical memory map.

4.

Supply and startup considerations: VDDIN is using GND as ground pin. Clarified references to 
PORs in startup considerations.

5.

FLASHCDW: Added serial number location to module configuration section.

6.

PM: Added more info about the WAKE_N pin. Added info about CLK_PM, Updated the 
selection main clock source section.

7.

SCIF: Major chapter update.

8.

AST: Updated digital tuner formula and conditions.

9.

GPIO: Updated GPER reset value and added more registers with non-zero reset value.

10.

CAT: Added info about VDIVEN and discharge current formula.

11.

ADCIFB: Fixed Sample and Hold time formula.

12.

GLOC: Added info about pullup control and renamed LUTCR register to CR.