Atmel Xplained Evaluation Board AT32UC3L0-XPLD AT32UC3L0-XPLD Data Sheet
Product codes
AT32UC3L0-XPLD
14
32099G–06/2011
AT32UC3L016/32/64
TMS
Test Mode Select
Input
Power Manager - PM
RESET_N
Reset
Input
Low
Pulse Width Modulation Controller - PWMA
PWMA35 - PWMA0
PWMA channel waveforms
Output
PWMAOD35 -
PWMAOD0
PWMAOD0
PWMA channel waveforms, open drain
mode
mode
Output
Not all channels support open
drain mode
drain mode
System Control Interface - SCIF
GCLK4 - GCLK0
Generic Clock Output
Output
RC32OUT
RC32K output at startup
Output
XIN0
Crystal 0 Input
Analog/
Digital
XIN32
Crystal 32 Input (primary location)
Analog/
Digital
XIN32_2
Crystal 32 Input (secondary location)
Analog/
Digital
XOUT0
Crystal 0 Output
Analog
XOUT32
Crystal 32 Output (primary location)
Analog
XOUT32_2
Crystal 32 Output (secondary location)
Analog
Serial Peripheral Interface - SPI
MISO
Master In Slave Out
I/O
MOSI
Master Out Slave In
I/O
NPCS3 - NPCS0
SPI Peripheral Chip Select
I/O
Low
SCK
Clock
I/O
Timer/Counter - TC0, TC1
A0
Channel 0 Line A
I/O
A1
Channel 1 Line A
I/O
A2
Channel 2 Line A
I/O
B0
Channel 0 Line B
I/O
B1
Channel 1 Line B
I/O
B2
Channel 2 Line B
I/O
CLK0
Channel 0 External Clock Input
Input
CLK1
Channel 1 External Clock Input
Input
CLK2
Channel 2 External Clock Input
Input
Two-wire Interface - TWIMS0, TWIMS1
TWALM
SMBus SMBALERT
I/O
Low
TWCK
Two-wire Serial Clock
I/O
TWD
Two-wire Serial Data
I/O
Table 3-7.
Signal Descriptions List