Atmel Xplained Evaluation Board AT32UC3L0-XPLD AT32UC3L0-XPLD Data Sheet
Product codes
AT32UC3L0-XPLD
34
32099G–06/2011
AT32UC3L016/32/64
5.4
CPU Local Bus Mapping
Some of the registers in the GPIO module are mapped onto the CPU local bus, in addition to
being mapped on the Peripheral Bus. These registers can therefore be reached both by
accesses on the Peripheral Bus, and by accesses on the local bus.
being mapped on the Peripheral Bus. These registers can therefore be reached both by
accesses on the Peripheral Bus, and by accesses on the local bus.
Mapping these registers on the local bus allows cycle-deterministic toggling of GPIO pins since
the CPU and GPIO are the only modules connected to this bus. Also, since the local bus runs at
CPU speed, one write or read operation can be performed per clock cycle to the local bus-
mapped GPIO registers.
the CPU and GPIO are the only modules connected to this bus. Also, since the local bus runs at
CPU speed, one write or read operation can be performed per clock cycle to the local bus-
mapped GPIO registers.
0xFFFF4800
TWIM1
Two-wire Master Interface - TWIM1
0xFFFF4C00
TWIS0
Two-wire Slave Interface - TWIS0
0xFFFF5000
TWIS1
Two-wire Slave Interface - TWIS1
0xFFFF5400
PWMA
Pulse Width Modulation Controller - PWMA
0xFFFF5800
TC0
Timer/Counter - TC0
0xFFFF5C00
TC1
Timer/Counter - TC1
0xFFFF6000
ADCIFB
ADC Interface - ADCIFB
0xFFFF6400
ACIFB
Analog Comparator Interface - ACIFB
0xFFFF6800
CAT
Capacitive Touch Module - CAT
0xFFFF6C00
GLOC
Glue Logic Controller - GLOC
0xFFFF7000
AW
aWire - AW
Table 5-3.
Peripheral Address Mapping