Atmel Xplained Evaluation Board AT32UC3L0-XPLD AT32UC3L0-XPLD Data Sheet
Product codes
AT32UC3L0-XPLD
5
32099G–06/2011
AT32UC3L016/32/64
2.
Overview
2.1
Block Diagram
Figure 2-1.
Block Diagram
SYSTEM CONTROL
INTERFACE
INTERRUPT
CONTROLLER
ASYNCHRONOUS
TIMER
PERIPHERAL
DMA
CONTROLLER
HSB-PB
BRIDGE B
HSB-PB
BRIDGE A
S
M
M
M
S
S
M
EXTERNAL INTERRUPT
CONTROLLER
HIGH SPEED
BUS MATRIX
BUS MATRIX
G
E
NE
RALPU
R
POSE
I/O
s
GENE
RAL P
URPOSE I
/Os
PA
PB
PB
EXTINT[5..1]
NMI
GCLK[4..0]
PA
PB
PB
SPI
DM
A
MISO, MOSI
NPCS[3..0]
USART0
USART1
USART2
USART3
USART1
USART2
USART3
DM
A
RXD
TXD
CLK
CLK
RTS, CTS
WATCHDOG
TIMER
SCK
JTAG
INTERFACE
MCKO
MDO[5..0]
MSEO[1..0]
EVTI_N
TDO
TDI
TMS
CONFIGURATION REGISTERS BUS
64/32/16 KB
FLASH
S
F
LASH
CONTR
O
LL
ER
EVTO_N
AVR32UC CPU
NEXUS
CLASS 2+
OCD
INSTR
INTERFACE
DATA
INTERFACE
ME
M
O
R
Y
INTE
RF
A
C
E
LOCAL BUS
16/8 KB
SRAM
MEMORY PROTECTION UNIT
LOCAL BUS
INTERFACE
INTERFACE
FREQUENCY METER
PWM CONTROLLER
PWMA[35..0]
TIMER/COUNTER 0
TIMER/COUNTER 1
TIMER/COUNTER 1
A[2..0]
B[2..0]
CLK[2..0]
TWI MASTER 0
TWI MASTER 1
TWI MASTER 1
DM
A
TWI SLAVE 0
TWI SLAVE 1
TWI SLAVE 1
DM
A
8-CHANNEL ADC
INTERFACE
DM
A
AD[8..0]
ADVREFP
POWER MANAGER
RESET
CONTROLLER
SLEEP
CONTROLLER
CLOCK
CONTROLLER
XIN32
XOUT32
OSC32K
RCSYS
XIN0
XOUT0
OSC0
DFLL
TCK
aWire
RESET_N
CAPACITIVE TOUCH
MODULE
DM
A
CSB[16:0]
SMP
CSA[16:0]
SYNC
AC INTERFACE
ACREFN
ACAN[3..0]
ACBN[3..0]
ACBP[3..0]
ACAP[3..0]
TWCK
TWD
TWALM
TWCK
TWD
TWALM
RC32K
RC120M
GLUE LOGIC
CONTROLLER
IN[7..0]
OUT[1:0]
DATAOUT
SAU
S/M
VDIVEN
DIS
PRND
TRIGGER
ADP[1..0]
RC32OUT