Atmel Xplained Evaluation Board AT32UC3L0-XPLD AT32UC3L0-XPLD Data Sheet
Product codes
AT32UC3L0-XPLD
66
32099G–06/2011
AT32UC3L016/32/64
Figure 7-12. USART in
SPI Slave Mode NPCS Timing
Notes:
1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-
cess technology. These values are not covered by test limits in production.
2. Where:
Maximum SPI Frequency, Slave Input Mode
The maximum SPI slave input frequency is given by the following formula:
Where
is the MOSI setup and hold time, USPI7 + USPI8 or USPI10 + USPI11 depending
on CPOL and NCPHA.
is the maximum frequency of the CLK_SPI. Refer to the SPI
chapter for a description of this clock.
Maximum SPI Frequency, Slave Output Mode
USPI14
USPI12
USPI15
USPI13
NSS
SPCK, CPOL=0
SPCK, CPOL=1
Table 7-39.
USART in SPI mode Timing, Slave Mode
Symbol
Parameter
Conditions
Min
Max
Units
USPI6
SPCK falling to MISO delay
V
VDDIO
from
3.0V to 3.6V,
maximum
external
capacitor =
40pF
27.6
ns
USPI7
MOSI setup time before SPCK rises
t
SAMPLE
+ t
CLK_USART
USPI8
MOSI hold time after SPCK rises
0
USPI9
SPCK rising to MISO delay
27.2
USPI10
MOSI setup time before SPCK falls
t
SAMPLE
+ t
CLK_USART
USPI11
MOSI hold time after SPCK falls
0
USPI12
NSS setup time before SPCK rises
25.0
USPI13
NSS hold time after SPCK falls
0
USPI14
NSS setup time before SPCK falls
25.0
USPI15
NSS hold time after SPCK rises
0
t
SAMPLE
t
SPCK
t
SPCK
2
t
CLKUSART
×
------------------------------------
1
2
2
---
+
⎝
⎠
⎛
⎞ t
CLKUSART
×
–
=
f
SPCKMAX
MIN
f
CLKSPI
2
×
9
-----------------------------
1
SPIn
------------
(
,
)
=
SPIn
f
CLKSPI