Atmel Xplained Evaluation Board AT32UC3L0-XPLD AT32UC3L0-XPLD Data Sheet

32099G–06/2011

Figure 7-16. SPI Slave Mode With (CPOL= NCPHA= 0) or (CPOL= NCPHA= 1)

Figure 7-17.  SPI Slave Mode NPCS Timing

Note:

1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-

cess technology. These values are not covered by test limits in production.

SPI10

SPI11

MISO

SPCK

MOSI

SPI9

SPI14

SPI12

SPI15

SPI13

NPCS

SPCK, CPOL=0

SPCK, CPOL=1

SPI Timing, Slave Mode

SPI6

SPCK falling to MISO delay

V

VDDIO 

from 

3.0V to 3.6V, 

maximum 

external 

capacitor = 

40pF

79.9

ns

SPI7

MOSI setup time before SPCK rises

49.4

SPI8

MOSI hold time after SPCK rises

4.1

SPI9

SPCK rising to MISO delay

80.8

SPI10

MOSI setup time before SPCK falls

48.8

SPI11

MOSI hold time after SPCK falls

3.5

SPI12

NPCS setup time before SPCK rises

4.9

SPI13

NPCS hold time after SPCK falls

2.7

SPI14

NPCS setup time before SPCK falls

3.8

SPI15

NPCS hold time after SPCK rises

3.2