Atmel Xplained Evaluation Board AT32UC3L0-XPLD AT32UC3L0-XPLD Data Sheet

32099G–06/2011

The DFLLIF dithering does not work. 
Fix/Workaround
None.

DFLLIF might lose fine lock when dithering is disabled
When dithering is disabled and fine lock has been acquired, the DFLL might lose the fine
lock resulting in up to 20% over-/undershoot.
Fix/Workaround
Solution 1: When the DFLL is used as main clock source, the target frequency of the DFLL
should be 20% below the maximum operating frequency of the CPU. Don’t use the DFLL as
clock source for frequency sensitive applications. 
Solution 2: Do not use the DFLL in closed loop mode.

GCLK5 is non-functional
GCLK5 is non-functional.
Fix/Workaround
None.

PCLKSR.OSC32RDY bit might not be cleared after disabling OSC32K
In some cases the OSC32RDY bit in the PCLKSR register will not be cleared when OSC32K
is disabled.
Fix/Workaround
When re-enabling the OSC32K, read the PCLKSR.OSC32RDY bit. If this bit is:
0: Follow normal procedures. 
1: Ignore the PCLKSR.OSC32RDY and ISR.OSC32RDY bit. Use the Frequency Meter
(FREQM) to determine if the OSC32K clock is ready. The OSC32K clock is ready when the
FREQM measures a non-zero frequency.

BRIFA is non-functional
BRIFA is non-functional.
Fix/Workaround
None.

SCIF VERSION register reads 0x100
SCIFVERSION register reads 0x100 instead of 0x102.
Fix/Workaround
None.

BODVERSION register reads 0x100
BODVERSION register reads 0x100 instead of 0x101.
Fix/Workaround
None.

DFLLVERSION register reads 0x200
DFLLVERSION register reads 0x200 instead of 0x201.
Fix/Workaround
None.

RCCRVERSION register reads 0x100
RCCRVERSION register reads 0x100 instead of 0x101.
Fix/Workaround
None.