Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet

ARM DDI0198D

Glossary-17

See  Test access port.

See Tightly coupled memory.

The collection of four mandatory and one optional terminals that form the input/output 
and control interface to a JTAG boundary-scan architecture. The mandatory terminals 
are TDI, TDO, TMS, and TCK. The optional terminal is TRST. This signal is 
mandatory in ARM cores because it is used to reset the debug logic.

A halfword that specifies an operation for an ARM processor in Thumb state to 
perform. Thumb instructions must be halfword-aligned.

A processor that is executing Thumb (16-bit) halfword aligned instructions is operating 
in Thumb state.

An area of low latency memory that provides predictable instruction execution or data 
load timing in cases where deterministic performance is required. TCMs are suited to 
holding:
- critical routines (such as for interrupt handling)
- scratchpad data
- data types whose locality is not suited to caching
- critical data structures (such as interrupt stacks).

See Translation Look-aside Buffer.

A cache of recently used page table entries that avoid the overhead of page table 
walking on every memory access. Part of the Memory Management Unit.

A table, held in memory, that contains data that defines the properties of memory areas 
of various fixed sizes.

The process of doing a full translation table lookup. It is performed automatically by 
hardware.

Indicates an instruction that generates an Undefined instruction trap. See the ARM 
Architecture Reference Manual for more details on ARM exceptions.

Means that the behavior of the ETM cannot be relied upon. Such conditions have not 
been validated. When applied to the programming of an event resource, only the output 
of that event resource is Unpredictable.

Unpredictable behavior can affect the behavior of the entire system, because the ETM 
is capable of causing the core to enter debug state, and external outputs may be used for 
other purposes.