Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
Programmer’s Model
ARM DDI0198D
Copyright © 2001-2003 ARM Limited. All rights reserved.
2-23
The MVA format for Rd for the CP15 c7 MCR operations is shown in Figure 2-9. The
Tag, Set, and Word fields define the MVA. For all of the cache operations, Word Should
Be Zero.
Tag, Set, and Word fields define the MVA. For all of the cache operations, Word Should
Be Zero.
Figure 2-9 Register c7 MVA format
The Set/Way format for Rd for the CP15 c7 MCR operations is shown in Figure 2-10
on page 2-24, where A and S are the base-two logarithms of the associativity and the
number of sets. The Set, Way, and Word fields define the format. For all of the cache
operations, Word Should Be Zero.
on page 2-24, where A and S are the base-two logarithms of the associativity and the
number of sets. The Set, Way, and Word fields define the format. For all of the cache
operations, Word Should Be Zero.
For a 16KB cache, 4-way set associative, 8-word line, then:
•
A = log
2
associativity = log
2
4 = 2
•
S = log
2
NSETS where:
NSETS= cache size in bytes/associativity/line length in bytes:
NSETS= 16384/4/32 = 128
Therefore:
S = log
2
128 = 7
Invalidate DCache single entry (Set/Way)
Set/Way
MCR p15, 0, <Rd>, c7, c6, 2
Clean DCache single entry (MVA)
MVA
MCR p15, 0, <Rd>, c7, c10, 1
Clean DCache single entry (Set/Way)
Set/Way
MCR p15, 0, <Rd>, c7, c10, 2
Test and clean DCache
-
MRC p15, 0, <Rd>, c7, c10, 3
Clean and invalidate DCache entry (MVA)
MVA
MCR p15, 0, <Rd>, c7, c14, 1
Clean and invalidate DCache entry (Set/Way)
Set/Way
MCR p15, 0, <Rd>, c7, c14, 2
Test, clean, and invalidate DCache
-
MRC p15, 0, <Rd>, c7, c14, 3
Drain write buffer
SBZ
MCR p15, 0, <Rd>, c7, c10, 4
Wait for interrupt
SBZ
MCR p15, 0, <Rd>, c7, c0, 4
Table 2-18 Cache operations c7 (continued)
Function/operation
Data format
Instruction
Tag
31
S+5 S+4
5 4
2 1 0
Set (= index)
Word
SBZ