Atmel Evaluation Kit AT91SAM9X35-EK AT91SAM9X35-EK Data Sheet
Product codes
AT91SAM9X35-EK
1116
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
0x00000114
Overlay 1 Interrupt Mask Register
LCDC_OVRIMR1
Read-only
0x00000000
0x00000118
Overlay 1 Interrupt Status Register
LCDC_OVRISR1
Read-only
0x00000000
0x0000011C
Overlay 1 DMA Head Register
LCDC_OVRHEAD1
Read-write
0x00000000
0x00000120
Overlay 1 DMA Address Register
LCDC_OVRADDR1
Read-write
0x00000000
0x00000124
Overlay1 DMA Control Register
LCDC_OVRCTRL1
Read-write
0x00000000
0x00000128
Overlay1 DMA Next Register
LCDC_OVRNEXT1
Read-write
0x00000000
0x0000012C
Overlay 1 Configuration 0 Register
LCDC_OVR1CFG0
Read-write
0x00000000
0x00000130
Overlay 1 Configuration 1 Register
LCDC_OVR1CFG1
Read-write
0x00000000
0x00000134
Overlay 1 Configuration 2 Register
LCDC_OVR1CFG2
Read-write
0x00000000
0x00000138
Overlay 1 Configuration 3 Register
LCDC_OVR1CFG3
Read-write
0x00000000
0x0000013C
Overlay 1 Configuration 4 Register
LCDC_OVR1CFG4
Read-write
0x00000000
0x00000140
Overlay 1 Configuration 5 Register
LCDC_OVR1CFG5
Read-write
0x00000000
0x00000144
Overlay 1 Configuration 6 Register
LCDC_OVR1CFG6
Read-write
0x00000000
0x00000148
Overlay 1 Configuration 7 Register
LCDC_OVR1CFG7
Read-write
0x00000000
0x0000014C
Overlay 1 Configuration 8 Register
LCDC_OVR1CFG8
Read-write
0x00000000
0x00000150
Overlay 1 Configuration 9 Register
LCDC_OVR1CFG9
Read-write
0x00000000
0x154-0x27C
Reserved
–
–
–
0x00000280
High End Overlay Channel Enable Register
LCDC_HEOCHER
Write-only
0x00000000
0x00000284
High End Overlay Channel Disable Register
LCDC_HEOCHDR
Write-only
0x00000000
0x00000288
High End Overlay Channel Status Register
LCDC_HEOCHSR
Read-only
0x00000000
0x0000028C
High End Overlay Interrupt Enable Register
LCDC_HEOIER
Write-only
0x00000000
0x00000290
High End Overlay Interrupt Disable Register
LCDC_HEOIDR
Write-only
0x00000000
0x00000294
High End Overlay Interrupt Mask Register
LCDC_HEOIMR
Read-only
0x00000000
0x00000298
High End Overlay Interrupt Status Register
LCDC_HEOISR
Read-only
0x00000000
0x0000029C
High End Overlay DMA Head Register
LCDC_HEOHEAD
Read-write
0x00000000
0x000002A0
High End Overlay DMA Address Register
LCDC_HEOADDR
Read-write
0x00000000
0x000002A4
High End Overlay DMA Control Register
LCDC_HEOCTRL
Read-write
0x00000000
0x000002A8
High End Overlay DMA Next Register
LCDC_HEONEXT
Read-write
0x00000000
0x000002AC
High End Overlay U DMA Head Register
LCDC_HEOUHEAD
Read-write
0x00000000
0x000002B0
High End Overlay U DMA Address Register
LCDC_HEOUADDR
Read-write
0x00000000
0x000002B4
High End Overlay U DMA Control Register
LCDC_HEOUCTRL
Read-write
0x00000000
0x000002B8
High End Overlay U DMA Next Register
LCDC_HEOUNEXT
Read-write
0x00000000
0x000002BC
High End Overlay V DMA Head Register
LCDC_HEOVHEAD
Read-write
0x00000000
0x000002C0
High End Overlay V DMA Address Register
LCDC_HEOVADDR
Read-write
0x00000000
0x000002C4
High End Overlay V DMA Control Register
LCDC_HEOVCTRL
Read-write
0x00000000
0x000002C8
High End Overlay VDMA Next Register
LCDC_HEOVNEXT
Read-write
0x00000000
0x000002CC
High End Overlay Configuration Register 0
LCDC_HEOCFG0
Read-write
0x00000000
0x000002D0
High End Overlay Configuration Register 1
LCDC_HEOCFG1
Read-write
0x00000000
0x000002D4
High End Overlay Configuration Register 2
LCDC_HEOCFG2
Read-write
0x00000000
Table 46-55. Register Mapping (Continued)
Offset
Register
Name
Access
Reset