Atmel Evaluation Kit AT91SAM9X35-EK AT91SAM9X35-EK Data Sheet
Product codes
AT91SAM9X35-EK
407
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
6.
An Extended Mode Register set (EMRS2) cycle is issued to chose between commercial or high temperature oper-
ations. The application must set Mode to 5 in the Mode Register (see
ations. The application must set Mode to 5 in the Mode Register (see
write access to the DDR2-SDRAM to acknowledge this command. The write address must be chosen so that
BA[1] is set to 1 and BA[0] is set to 0. For example, with a 16-bit 128 MB DDR2-SDRAM (12 rows, 9 columns, 4
banks) bank address, the DDR2-SDRAM write access should be done at the address 0x20800000.
BA[1] is set to 1 and BA[0] is set to 0. For example, with a 16-bit 128 MB DDR2-SDRAM (12 rows, 9 columns, 4
banks) bank address, the DDR2-SDRAM write access should be done at the address 0x20800000.
Note:
This address is for example purposes only. The real address is dependent on implementation in the product.
7.
An Extended Mode Register set (EMRS3) cycle is issued to set the Extended Mode Register to “0”. The applica-
tion must set Mode to 5 in the Mode Register (see
tion must set Mode to 5 in the Mode Register (see
) and perform a write access to the
DDR2-SDRAM to acknowledge this command. The write address must be chosen so that BA[1] is set to 1 and
BA[0] is set to 1. For example, with a 16-bit 128 MB DDR2-SDRAM (12 rows, 9 columns, 4 banks) bank address,
the DDR2-SDRAM write access should be done at the address 0x20C00000.
BA[0] is set to 1. For example, with a 16-bit 128 MB DDR2-SDRAM (12 rows, 9 columns, 4 banks) bank address,
the DDR2-SDRAM write access should be done at the address 0x20C00000.
8.
An Extended Mode Register set (EMRS1) cycle is issued to enable DLL. The application must set Mode to 5 in the
Mode Register (see
Mode Register (see
) and perform a write access to the DDR2-SDRAM to acknowl-
edge this command. The write address must be chosen so that BA[1] is set to 0 and BA[0] is set to 1. For example,
with a 16-bit 128 MB DDR2-SDRAM (12 rows, 9 columns, 4 banks) bank address, the DDR2-SDRAM write access
should be done at the address 0x20400000.
with a 16-bit 128 MB DDR2-SDRAM (12 rows, 9 columns, 4 banks) bank address, the DDR2-SDRAM write access
should be done at the address 0x20400000.
An additional 200 cycles of clock are required for locking DLL
9.
Program DLL field into the Configuration Register (see
) to high (Enable DLL reset).
10. A Mode Register set (MRS) cycle is issued to reset DLL. The application must set Mode to 3 in the Mode Register
) and perform a write access to the DDR2-SDRAM to acknowledge this com-
mand. The write address must be chosen so that BA[1:0] bits are set to 0. For example, with a 16-bit 128 MB
DDR2-SDRAM (12 rows, 9 columns, 4 banks) bank address, the SDRAM write access should be done at the
address 0x20000000.
DDR2-SDRAM (12 rows, 9 columns, 4 banks) bank address, the SDRAM write access should be done at the
address 0x20000000.
11. An all banks precharge command is issued to the DDR2-SDRAM. Program all banks precharge command into the
Mode Register, the application must set Mode to 2 in the Mode Register (See
form a write access to any DDR2-SDRAM address to acknowledge this command
12. Two auto-refresh (CBR) cycles are provided. Program the auto refresh command (CBR) into the Mode Register,
). Performs a write
access to any DDR2-SDRAM location twice to acknowledge these commands.
13. Program DLL field into the Configuration Register (see
) to low (Disable DLL reset).
14. A Mode Register set (MRS) cycle is issued to program the parameters of the DDR2-SDRAM devices, in particular
CAS latency, burst length and to disable DLL reset. The application must set Mode to 3 in the Mode Register (see
) and perform a write access to the DDR2-SDRAM to acknowledge this command. The
write address must be chosen so that BA[1:0] are set to 0. For example, with a 16-bit 128 MB SDRAM (12 rows, 9
columns, 4 banks) bank address, the SDRAM write access should be done at the address 0x20000000
columns, 4 banks) bank address, the SDRAM write access should be done at the address 0x20000000
) to high (OCD calibration
default).
16. An Extended Mode Register set (EMRS1) cycle is issued to OCD default value. The application must set Mode to
5 in the Mode Register (see
) and perform a write access to the DDR2-SDRAM to
acknowledge this command. The write address must be chosen so that BA[1] is set to 0 and BA[0] is set to 1. For
example, with a 16-bit 128 MB DDR2-SDRAM (12 rows, 9 columns, 4 banks) bank address, the DDR2-SDRAM
write access should be done at the address 0x20400000.
example, with a 16-bit 128 MB DDR2-SDRAM (12 rows, 9 columns, 4 banks) bank address, the DDR2-SDRAM
write access should be done at the address 0x20400000.
17. Program OCD field into the Configuration Register (see
) to low (OCD calibration mode
exit).
18. An Extended Mode Register set (EMRS1) cycle is issued to enable OCD exit. The application must set Mode to 5
in the Mode Register (see
) and perform a write access to the DDR2-SDRAM to
acknowledge this command. The write address must be chosen so that BA[1] is set to 0 and BA[0] is set to 1. For
example, with a 16-bit 128 MB DDR2-SDRAM (12 rows, 9 columns, 4 banks) bank address, the DDR2-SDRAM
write access should be done at the address 0x20400000.
example, with a 16-bit 128 MB DDR2-SDRAM (12 rows, 9 columns, 4 banks) bank address, the DDR2-SDRAM
write access should be done at the address 0x20400000.