Atmel Evaluation Kit AT91SAM9X35-EK AT91SAM9X35-EK Data Sheet

Product codes
AT91SAM9X35-EK
Page of 1301
443
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
30.7.10 DDRSDRC High Speed Register
Name:
DDRSDRC_HS
Address:
0xFFFFE82C
Access:
Read-write
Reset:
See 
This register can only be written if the bit WPEN is cleared in 
.
• DIS_ANTICIP_READ: Anticip Read Access
0 = anticip read access is enabled.
1 = anticip read access is disabled (default).
DIS_ANTICIP_READ allows DDR2 read access optimization with multi-port.
As this feature is based on the “bank open policy”, the software must map different buffers in different DDR2 banks to take advan-
tage of that feature.
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0
DIS_ANTICIP_RE
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