Atmel Evaluation Kit AT91SAM9X35-EK AT91SAM9X35-EK Data Sheet

447

SAM9X35 [DATASHEET]

11055E–ATARM–10-Mar-2014



Two Masters



Embeds 8 channels



64-byte FIFO for channel 0, 16-byte FIFO for Channel 1 to 7



Features:



Linked List support with Status Write Back operation at End of Transfer



Word, HalfWord, Byte transfer support.



Memory to memory transfer



Peripheral to memory



Memory to peripheral

The DMA controller can handle the transfer between peripherals and memory and so receives the triggers from the 
peripherals below. The hardware interface numbers are provided in 

.

RX/TX

0

TX

1

RX

2

TX

3

RX

4

TX

5

RX

6

TX

7

RX

8

TX

9

RX

10

TX

11

RX

12

TX

13

RX

14