Atmel Evaluation Kit AT91SAM9X35-EK AT91SAM9X35-EK Data Sheet
Product codes
AT91SAM9X35-EK
510
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
4.
If the user chooses to reconfigure the endpoint 3 with a larger size, the controller allocates a memory area after the
endpoint 2 memory area and automatically slides up the endpoint 4 memory window. The endpoint 5 does not
move and a memory conflict appears as the memory windows of the endpoints 4 and 5 overlap. The data of these
endpoints is potentially lost.
endpoint 2 memory area and automatically slides up the endpoint 4 memory window. The endpoint 5 does not
move and a memory conflict appears as the memory windows of the endpoints 4 and 5 overlap. The data of these
endpoints is potentially lost.
Notes: 1. There is no way the data of the endpoint 0 can be lost (except if it is de-allocated) as the memory allocation
and de-allocation may affect only higher endpoints.
2. Deactivating then reactivating the same endpoint with the same configuration only modifies temporarily the
controller DPRAM pointer and size for this endpoint. Nothing changes in the DPRAM, higher endpoints
seem not to have been moved and their data is preserved as far as nothing has been written or received into
them while changing the allocation state of the first endpoint.
seem not to have been moved and their data is preserved as far as nothing has been written or received into
them while changing the allocation state of the first endpoint.
3. When the user writes a value different from zero to the UDPHS_EPTCFGx.BK_NUMBER field, the Endpoint
Mapped bit (UDPHS_EPTCFGx.EPT_MAPD) is set only if the configured size and number of banks are cor-
rect as compared to the endpoint maximal allowed values and to the maximal FIFO size (i.e. the DPRAM
size). The UDPHS_EPTCFGx.EPT_MAPD value does not consider memory allocation conflicts.
rect as compared to the endpoint maximal allowed values and to the maximal FIFO size (i.e. the DPRAM
size). The UDPHS_EPTCFGx.EPT_MAPD value does not consider memory allocation conflicts.
32.6.8 Transfer With DMA
USB packets of any length may be transferred when required by the UDPHS Device. These transfers always feature
sequential addressing.
sequential addressing.
Packet data AHB bursts may be locked on a DMA buffer basis for drastic overall AHB bus bandwidth performance boost
with paged memories. These clock-cycle consuming memory row (or bank) changes will then likely not occur, or occur
only once instead of dozens times, during a single big USB packet DMA transfer in case another AHB master addresses
the memory. This means up to 128-word single-cycle unbroken AHB bursts for Bulk endpoints and 256-word single-cycle
unbroken bursts for isochronous endpoints. This maximum burst length is then controlled by the lowest programmed
USB endpoint size (EPT_SIZE field in the UDPHS_EPTCFGx register) and DMA Size (BUFF_LENGTH field in the
UDPHS_DMACONTROLx register).
with paged memories. These clock-cycle consuming memory row (or bank) changes will then likely not occur, or occur
only once instead of dozens times, during a single big USB packet DMA transfer in case another AHB master addresses
the memory. This means up to 128-word single-cycle unbroken AHB bursts for Bulk endpoints and 256-word single-cycle
unbroken bursts for isochronous endpoints. This maximum burst length is then controlled by the lowest programmed
USB endpoint size (EPT_SIZE field in the UDPHS_EPTCFGx register) and DMA Size (BUFF_LENGTH field in the
UDPHS_DMACONTROLx register).
The USB 2.0 device average throughput may be up to nearly 60 MBytes. Its internal slave average access latency
decreases as burst length increases due to the 0 wait-state side effect of unchanged endpoints. If at least 0 wait-state
word burst capability is also provided by the external DMA AHB bus slaves, each of both DMA AHB busses need less
than 50% bandwidth allocation for full USB 2.0 bandwidth usage at 30 MHz, and less than 25% at 60 MHz.
decreases as burst length increases due to the 0 wait-state side effect of unchanged endpoints. If at least 0 wait-state
word burst capability is also provided by the external DMA AHB bus slaves, each of both DMA AHB busses need less
than 50% bandwidth allocation for full USB 2.0 bandwidth usage at 30 MHz, and less than 25% at 60 MHz.
The UDPHS DMA Channel Transfer Descriptor is described in
.
Note:
In case of debug, be careful to address the DMA to an SRAM address even if a remap is done.