Atmel Evaluation Kit AT91SAM9X35-EK AT91SAM9X35-EK Data Sheet

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SAM9X35 [DATASHEET]

11055E–ATARM–10-Mar-2014

0 = If cleared, this bit lets the hardware handle the handshake response for the High Speed Bulk OUT transfer.

1 = If set, this bit forces an ACK response to the next High Speed Bulk OUT transfer instead of a NYET response.
Note:

According to the Universal Serial Bus Specification, Rev 2.0 (8.5.1.1 NAK Responses to OUT/DATA During PING 
Protocol), a NAK response to an HS Bulk OUT transfer is expected to be an unusual occurrence.

0 = Overflow Error Interrupt is masked.

1 = Overflow Error Interrupt is enabled.

0 = Received OUT Data Interrupt is masked.

1 = Received OUT Data Interrupt is enabled.

0 = Transmitted IN Data Complete Interrupt is masked.

1 = Transmitted IN Data Complete Interrupt is enabled.

0 = TX Packet Ready Interrupt is masked.

1 = TX Packet Ready Interrupt is enabled.

Caution: Interrupt source is active as long as the corresponding UDPHS_EPTSTAx register TXRDY flag remains low. If
there are no more banks available for transmitting after the software has set UDPHS_EPTSTAx/TXRDY for the last
transmit packet, then the interrupt source remains inactive until the first bank becomes free again to transmit at
UDPHS_EPTSTAx/TXRDY hardware clear.

0 = Received SETUP is masked.
1 = Received SETUP is enabled.

0 = Stall Sent Interrupt is masked.
1 = Stall Sent Interrupt is enabled.

0 = NAKIN Interrupt is masked.
1 = NAKIN Interrupt is enabled.

0 = NAKOUT Interrupt is masked.
1 = NAKOUT Interrupt is enabled.

0 = BUSY_BANK Interrupt is masked.
1 = BUSY_BANK Interrupt is enabled.

For OUT endpoints: an interrupt is sent when all banks are busy.

For IN endpoints: an interrupt is sent when all banks are free.