Atmel Evaluation Kit AT91SAM9X35-EK AT91SAM9X35-EK Data Sheet
Product codes
AT91SAM9X35-EK
552
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
If the exception raised is not associated to a new system bank packet (ex:ERR_FL_ISO), then the request cancellation may hap-
pen at any time and may immediately stop the current DMA transfer.
pen at any time and may immediately stop the current DMA transfer.
This may be used, for example, to identify or prevent an erroneous packet to be transferred into a buffer or to complete a DMA
buffer by software after reception of a short packet, or to perform buffer truncation on ERR_FL_ISO interrupt for adaptive rate.
buffer by software after reception of a short packet, or to perform buffer truncation on ERR_FL_ISO interrupt for adaptive rate.
• DATAX_RX: DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)
0 = No effect.
1 = Send an interrupt when a DATA2, DATA1 or DATA0 packet has been received meaning the whole microframe data payload
has been received.
has been received.
• MDATA_RX: MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)
0 = No effect.
1 = Send an interrupt when an MDATA packet has been received and so at least one packet of the microframe data payload has
been received.
been received.
• ERR_OVFLW: Overflow Error Interrupt Enabled
0 = Overflow Error Interrupt is masked.
1 = Overflow Error Interrupt is enabled.
• RXRDY_TXKL: Received OUT Data Interrupt Enabled
0 = Received OUT Data Interrupt is masked.
1 = Received OUT Data Interrupt is enabled.
• TX_COMPLT: Transmitted IN Data Complete Interrupt Enabled
0 = Transmitted IN Data Complete Interrupt is masked.
1 = Transmitted IN Data Complete Interrupt is enabled.
• TXRDY_TRER: TX Packet Ready/Transaction Error Interrupt Enabled
0 = TX Packet Ready/Transaction Error Interrupt is masked.
1 = TX Packet Ready/Transaction Error Interrupt is enabled.
Caution: Interrupt source is active as long as the corresponding UDPHS_EPTSTAx register TXRDY_TRER flag
r e m a i n s l o w . I f t h e r e a r e n o m o r e b a n k s a v a i l a b l e f o r t r a n s m i t t i n g a f t e r t h e s o f t w a r e h a s s e t
UDPHS_EPTSTAx/TXRDY_TRER for the last transmit packet, then the interrupt source remains inactive until the first
bank becomes free again to transmit at UDPHS_EPTSTAx/TXRDY_TRER hardware clear.
r e m a i n s l o w . I f t h e r e a r e n o m o r e b a n k s a v a i l a b l e f o r t r a n s m i t t i n g a f t e r t h e s o f t w a r e h a s s e t
UDPHS_EPTSTAx/TXRDY_TRER for the last transmit packet, then the interrupt source remains inactive until the first
bank becomes free again to transmit at UDPHS_EPTSTAx/TXRDY_TRER hardware clear.
• ERR_FL_ISO: Error Flow Interrupt Enabled
0 = Error Flow Interrupt is masked.
1 = Error Flow Interrupt is enabled.
• ERR_CRC_NTR: ISO CRC Error/Number of Transaction Error Interrupt Enabled
0 = ISO CRC error/number of Transaction Error Interrupt is masked.
1 = ISO CRC error/number of Transaction Error Interrupt is enabled.
• ERR_FLUSH: Bank Flush Error Interrupt Enabled
0 = Bank Flush Error Interrupt is masked.
1 = Bank Flush Error Interrupt is enabled.