Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO Data Sheet

1017

SAM4E [DATASHEET]

Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14

The PWM macrocell controls 4 channels independently. Each channel controls two complementary square output
waveforms. Characteristics of the output waveforms such as period, duty-cycle, polarity and dead-times (also
called dead-bands or non-overlapping times) are configured through the user interface. Each channel selects and
uses one of the clocks provided by the clock generator. The clock generator provides several clocks resulting from
the division of the PWM peripheral clock.

Each channel includes a register in order to generate an additional edge of the output waveform in addition of
those resulting of the duty cycle value.

All PWM macrocell accesses are made through registers mapped on the peripheral bus. All channels integrate a
double buffering system in order to

 

prevent

 

an unexpected output waveform while modifying the period, the spread

spectrum, the duty-cycle, the additional edge register or the dead-times.

Channels can be linked together as synchronous channels to be able to update their duty-cycle or dead-times at
the same time.

The update of duty-cycles of synchronous channels can be performed by the DMA Controller Channel (PDC or
DMA) which offers buffer transfer without processor Intervention.

The PWM macrocell includes a spread-spectrum counter to allow a constantly varying period (only for Channel 0).
This counter may be useful to minimize electromagnetic interference or to reduce the acoustic noise of a PWM
driven motor.

The PWM macrocell provides 8 independent comparison units capable of comparing a programmed value to the
counter of the synchronous channels (counter of channel 0). These comparisons are intended to generate
software interrupts, to trigger pulses on the 2 independent event lines (in order to synchronize ADC conversions
with a lot of flexibility independently of the PWM outputs) and to trigger PDC or DMAtransfer requests.

The PWM outputs can be overridden synchronously or asynchronously to their channel counter.

The PWM block provides a fault protection mechanism with

8

 

fault inputs

capable to detect a fault condition and to

override the PWM outputs asynchronously (outputs forced to ‘0’, ‘1’ or Hi-Z).

For safety usage, some configuration registers are write-protected.