Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO Data Sheet
Product codes
ATSAM4E-XPRO
1025
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
40.6.2.2 Comparator
The comparator continuously compares its counter value with the channel period defined by CPRD in the
(PWM_CPRDx) and the duty-cycle defined by CDTY in the
(PWM_CDTYx) to generate an output signal OCx accordingly.
The different properties of the waveform of the output OCx are:
the clock selection. The channel counter is clocked by one of the clocks provided by the clock generator
described in the previous section. This channel parameter is defined in the CPRE field of the
described in the previous section. This channel parameter is defined in the CPRE field of the
(PWM_CMRx). This field is reset at ‘0’.
the waveform period. This channel parameter is defined in the CPRD field of the PWM_CPRDx register.
If the waveform is left-aligned, then the output waveform period depends on the counter source clock and
can be calculated:
By using the PWM peripheral clock divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64,
128, 256, 512, or 1024), the resulting period formula will be:
If the waveform is left-aligned, then the output waveform period depends on the counter source clock and
can be calculated:
By using the PWM peripheral clock divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64,
128, 256, 512, or 1024), the resulting period formula will be:
By using the PWM peripheral clock divided by one of both DIVA or DIVB divider, the formula becomes,
respectively:
respectively:
or
If the waveform is center-aligned then the output waveform period depends on the counter source clock and
can be calculated:
By using the PWM peripheral clock divided by an X given prescaler value
(with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula will be:
can be calculated:
By using the PWM peripheral clock divided by an X given prescaler value
(with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula will be:
By using the PWM peripheral clock divided by one of both DIVA or DIVB divider, the formula becomes,
respectively:
respectively:
or
the waveform duty-cycle. This channel parameter is defined in the CDTY field of the PWM_CDTYx
register.
If the waveform is left-aligned then:
register.
If the waveform is left-aligned then:
If the waveform is center-aligned, then:
X
CPRD
×
(
)
f
peripheral clock
--------------------------------
X
C
× RPD DIVA
×
(
)
f
peripheral clock
----------------------------------------------------
X
C
× RPD DIVB
×
(
)
f
peripheral clock
----------------------------------------------------
2
X
CPRD
×
×
(
)
f
peripheral clock
----------------------------------------
2
X
C
× PRD DIVA
×
×
(
)
f
peripheral clock
-------------------------------------------------------------
2
X
C
× PRD
×
DIVB
×
(
)
f
peripheral clock
-------------------------------------------------------------
duty cycle
period
1 fchannel_x_clock
CDTY
×
⁄
–
(
)
period
----------------------------------------------------------------------------------------------------
=
duty cycle
period 2
⁄
(
) 1 fchannel_x_clock CDTY
×
⁄
–
(
) )
period 2
⁄
(
)
-------------------------------------------------------------------------------------------------------------------
=