Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO Data Sheet
Product codes
ATSAM4E-XPRO
1193
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
43.4
Signal Interface
The GMAC includes the following signal interfaces
MII, to an external PHY
MDIO interface for external PHY management
Slave APB interface for accessing GMAC registers
Master AHB interface for memory access
43.5
Functional Description
43.5.1 Media Access Controller
The Media Access Controller (MAC) transmit block takes data from FIFO, adds preamble and, if necessary, pad
and frame check sequence (FCS). Both half duplex and full duplex Ethernet modes of operation are supported.
When operating in half duplex mode, the MAC transmit block generates data according to the carrier sense
multiple access with collision detect (CSMA/CD) protocol. The start of transmission is deferred if carrier sense
(CRS) is active. If collision (COL) becomes active during transmission, a jam sequence is asserted and the
transmission is retried after a random back off. The CRS and COL signals have no effect in full duplex mode.
and frame check sequence (FCS). Both half duplex and full duplex Ethernet modes of operation are supported.
When operating in half duplex mode, the MAC transmit block generates data according to the carrier sense
multiple access with collision detect (CSMA/CD) protocol. The start of transmission is deferred if carrier sense
(CRS) is active. If collision (COL) becomes active during transmission, a jam sequence is asserted and the
transmission is retried after a random back off. The CRS and COL signals have no effect in full duplex mode.
The MAC receive block checks for valid preamble, FCS, alignment and length, and presents received frames to
the MAC address checking block and FIFO. Software can configure the GMAC to receive jumbo frames up to
10240 bytes. It can optionally strip CRC from the received frame prior to transfer to FIFO.
the MAC address checking block and FIFO. Software can configure the GMAC to receive jumbo frames up to
10240 bytes. It can optionally strip CRC from the received frame prior to transfer to FIFO.
The address checker recognizes four specific 48-bit addresses, can recognize four different type ID values, and
contains a 64-bit Hash Register for matching multicast and unicast addresses as required. It can recognize the
broadcast address of all ones and copy all frames. The MAC can also reject all frames that are not VLAN tagged
and recognize Wake on LAN events.
contains a 64-bit Hash Register for matching multicast and unicast addresses as required. It can recognize the
broadcast address of all ones and copy all frames. The MAC can also reject all frames that are not VLAN tagged
and recognize Wake on LAN events.
The MAC receive block supports offloading of IP, TCP and UDP checksum calculations (both IPv4 and IPv6
packet types supported), and can automatically discard bad checksum frames.
packet types supported), and can automatically discard bad checksum frames.
Table 43-1.
GMAC connections in the different modes
Signal Name
Function
MII
GTXCK
Transmit Clock or Reference Clock
TXCK
GTXEN
Transmit Enable
TXEN
GTX[3..0]
Transmit Data
TXD[3:0]
GTXER
Transmit Coding Error
TXER
GRXCK
Receive Clock
RXCK
GRXDV
Receive Data Valid
RXDV
GRX[3..0]
Receive Data
RXD[3:0]
GRXER
Receive Error
RXER
GCRS
Carrier Sense and Data Valid
CRS
GCOL
Collision Detect
COL
GMDC
Management Data Clock
MDC
GMDIO
Management Data Input/Output
MDIO