Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO Data Sheet

1209

SAM4E [DATASHEET]

Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14

The timer is implemented as a 62-bit register with the upper 32 bits counting seconds and the lower 30 bits
counting nanoseconds. The lower 30 bits roll over when they have counted to one second. An interrupt is
generated when the seconds increment. The timer value can be read, written and adjusted through the APB
interface.

The timer is clocked by MCK.

The amount by which the timer increments each clock cycle is controlled by the timer increment register. Bits [7:0]
are the default increment value in nanoseconds. If the rest of the register is written with zero the timer increments
by the value in [7:0] each clock cycle.

Bits [15:8] of the increment register are the alternative increment value in nanoseconds and bits [23:16] are the
number of increments after which the alternative increment value is used. If [23:16] are zero then the alternative
increment value will never be used.

Taking the example of 10.2 MHz, there are 102 cycles every ten microseconds or 51 every five microseconds. So
a timer with a 10.2 MHz clock source is constructed by incrementing by 98 ns for fifty cycles and then incrementing
by 100 ns (98 

× 50 + 100 = 5000). This is programmed by setting the 1588 Timer Increment Register to

0x00326462.

For a 49.8 MHz clock source it would be 20 ns for 248 cycles followed by an increment of 40 ns (20 

× 248 + 40 =

5000) programmed as 0x00F82814.

Having eight bits for the “number of increments” field allows frequencies up to 50 MHz to be supported with 200
kHz resolution.

Without the alternative increment field the period of the clock would be limited to an integer number of
nanoseconds, resulting in supported clock frequencies of 8, 10, 20, 25, 40, 50, 100, 125, 200 and 250 MHz.

GMAC is configured to operate as PTP slave. The timer register increments as normal but the timer value is
copied to the sync strobe register.

There are six additional 62-bit registers that capture the time at which PTP event frames are transmitted and
received. An interrupt is issued when these registers are updated.

Note:

See Clause 31, and Annex 31A and 31B of the IEEE standard 802.3 for a full description of MAC 802.3 pause 
operation. 

The following table shows the start of a MAC 802.3 pause frame.

The GMAC supports both hardware controlled pause of the transmitter, upon reception of a pause frame, and
hardware generated pause frame transmission.

Bit 13 of the Network Configuration Register is the pause enable control for reception. If this bit is set, transmission
will pause if a non zero pause quantum frame is received.

If a valid pause frame is received then the Pause Time Register is updated with the new frame's pause time,
regardless of whether a previous pause frame is active or not. An interrupt (either bit 12 or bit 13 of the Interrupt
Status Register) is triggered when a pause frame is received, but only if the interrupt has been enabled (bit 12 and
bit 13 of the Interrupt Mask Register). Pause frames received with non zero quantum are indicated through the

0x0180C2000001

6 bytes

0x8808

0x0001

2 bytes