Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO Data Sheet

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SAM4E [DATASHEET]

Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14

At reset all interrupts are disabled. To enable an interrupt, write to Interrupt Enable Register with the pertinent
interrupt bit set to 1. To disable an interrupt, write to Interrupt Disable Register with the pertinent interrupt bit set to
1. To check whether an interrupt is enabled or disabled, read Interrupt Mask Register. If the bit is set to 1, the
interrupt is disabled.

To set up a frame for transmission:

1.

Enable transmit in the Network Control Register.

2.

Allocate an area of system memory for transmit data. This does not have to be contiguous, varying byte 
lengths can be used if they conclude on byte borders.

3.

Set-up the transmit buffer list by writing buffer addresses to word zero of the transmit buffer descriptor 
entries and control and length to word one.

4.

Write data for transmission into the buffers pointed to by the descriptors.

5.

Write the address of the first buffer descriptor to transmit buffer descriptor queue pointer.

6.

Enable appropriate interrupts.

7.

Write to the transmit start bit (TSTART) in the Network Control Register.

When a frame is received and the receive circuits are enabled, the GMAC checks the address and, in the following
cases, the frame is written to system memory:



If it matches one of the four Specific Address Registers.



If it matches one of the four type ID registers.



If it matches the hash address function.



If it is a broadcast address (0xFFFFFFFFFFFF) and broadcasts are allowed.



If the GMAC is configured to “copy all frames”.

The register receive buffer queue pointer points to the next entry in the receive buffer descriptor list and the GMAC
uses this as the address in system memory to write the frame to. 

Once the frame has been completely and successfully received and written to system memory, the GMAC then
updates the receive buffer descriptor entry (see 

) with the reason for

the address match and marks the area as being owned by software. Once this is complete, a receive complete
interrupt is set. Software is then responsible for copying the data to the application area and releasing the buffer
(by writing the ownership bit back to 0).

If the GMAC is unable to write the data at a rate to match the incoming frame, then a receive overrun interrupt is
set. If there is no receive buffer available, i.e., the next buffer is still owned by software, a receive buffer not
available interrupt is set. If the frame is not successfully received, a statistics register is incremented and the frame
is discarded without informing software.

Statistics registers are described in the User Interface beginning with 

 and ending

with 

.

The statistics register block begins at 0x100 and runs to 0x1B0, and comprises the registers listed below.

Octets Transmitted [31:0] Register

Broadcast Frames Received Register

Octets Transmitted [47:32] Register

Multicast Frames Received Register

Frames Transmitted Register

Pause Frames Received Register

Broadcast Frames Transmitted Register

64 Byte Frames Received Register

Multicast Frames Transmitted Register

65 to 127 Byte Frames Received Register