Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO Data Sheet

SAM4E [DATASHEET]

Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14

1240

GMAC_IMR

0x40034030

Access: Read-only

The Interrupt Mask Register is a read-only register indicating which interrupts are masked. All bits are set at reset and can 
be reset individually by writing to the Interrupt Enable Register or set individually by writing to the Interrupt Disable Regis-
ter. Having separate address locations for enable and disable saves the need for performing a read modify write when 
updating the Interrupt Mask Register.

For test purposes there is a write-only function to this register that allows the bits in the Interrupt Status Register to be set 
or cleared, regardless of the state of the mask register.



A read of this register returns the value of the management done interrupt mask.

0: Interrupt is enabled.

1: Interrupt is disabled.

A write to this register directly affects the state of the corresponding bit in the Interrupt Status Register, causing an interrupt 
to be generated if a 1 is written.



A read of this register returns the value of the receive complete interrupt mask.

0: Interrupt is enabled.

1: Interrupt is disabled.

A write to this register directly affects the state of the corresponding bit in the Interrupt Status Register, causing an interrupt 
to be generated if a 1 is written.



A read of this register returns the value of the receive used bit read interrupt mask.

0: Interrupt is enabled.

1: Interrupt is disabled.

A write to this register directly affects the state of the corresponding bit in the Interrupt Status Register, causing an interrupt 
to be generated if a 1 is written.

31

30

29

28

27

26

25

24

–

–

–

–

–

–

PDRSFT

PDRQFT

23

22

21

20

19

18

17

16

PDRSFR

PDRQFR

SFT

DRQFT

SFR

DRQFR

–

–

15

14

13

12

11

10

9

8

EXINT

PFTR

PTZ

PFNZ

HRESP

ROVR

–

–

7

6

5

4

3

2

1

0

TCOMP

TFC

RLEX TUR

TXUBR

RXUBR

RCOMP

MFS