Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO Data Sheet
Product codes
ATSAM4E-XPRO
1245
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
43.7.14 PHY Maintenance Register
Name:
GMAC_MAN
Address:
0x40034034
Access: Read/Write
The PHY Maintenance Register is implemented as a shift register. Writing to the register starts a shift operation which is
signalled as complete when bit 2 is set in the Network Status Register. It takes about 2000 MCK cycles to complete, when
MDC is set for MCK divide by 32 in the Network Configuration Register. An interrupt is generated upon completion.
signalled as complete when bit 2 is set in the Network Status Register. It takes about 2000 MCK cycles to complete, when
MDC is set for MCK divide by 32 in the Network Configuration Register. An interrupt is generated upon completion.
During this time, the MSB of the register is output on the MDIO pin and the LSB updated from the MDIO pin with each MDC
cycle. This causes transmission of a PHY management frame on MDIO. See Section 22.2.4.5 of the IEEE 802.3 standard.
cycle. This causes transmission of a PHY management frame on MDIO. See Section 22.2.4.5 of the IEEE 802.3 standard.
Reading during the shift operation returns the current contents of the shift register. At the end of management operation,
the bits will have shifted back to their original locations. For a read operation, the data bits are updated with data read from
the PHY. It is important to write the correct values to the register to ensure a valid PHY management frame is produced.
the bits will have shifted back to their original locations. For a read operation, the data bits are updated with data read from
the PHY. It is important to write the correct values to the register to ensure a valid PHY management frame is produced.
The MDIO interface can read IEEE 802.3 clause 45 PHYs as well as clause 22 PHYs. To read clause 45 PHYs, bit 30
should be written with a 0 rather than a 1.
should be written with a 0 rather than a 1.
For a description of MDC generation, see
DATA: PHY Data
For a write operation this field is written with the data to be written to the PHY. After a read operation this field contains the
data read from the PHY.
data read from the PHY.
WTN: Write Ten
Must be written to 10.
REGA: Register Address
Specifies the register in the PHY to access.
PHYA: PHY Address
OP: Operation
01: Write
10: Read
CLTTO: Clause 22 Operation
Must be written to 1 for Clause 22 operation. To read clause 45 PHYs, bit 30 should be written with a 0 rather than a 1.
31
30
29
28
27
26
25
24
WZO
CLTTO
OP
PHYA
23
22
21
20
19
18
17
16
PHYA
REGA
WTN
15
14
13
12
11
10
9
8
DATA
7
6
5
4
3
2
1
0
DATA