Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO Data Sheet

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SAM4E [DATASHEET]

Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14

The conversion results can be signed (2’s complement) or unsigned depending on the value of the SIGNMODE
field of the AFEC_EMR (see 

). 

Four modes are available:



Results of channels configured in single-ended mode are unsigned, results of channels configured in 
differential mode are signed.



Results of channels configured in single-ended mode are signed, results of channels configured in 
differential mode are unsigned.



All channels results are unsigned.



All channels results are signed.

If conversion results are signed and resolution is below 16-bit, the sign is extended up to the bit 15 (for example,
0xF43 for 12-bit resolution will be read as 0xFF43 and 0x467 will be read as 0x0467).

Conversions of the active analog channels are started with a software or hardware trigger. The software trigger is
provided by writing the Control Register (AFEC_CR) with the START bit at 1. 

The hardware trigger can be one of the TIOA outputs of the Timer Counter channels, PWM Event line, or the
external trigger input of the AFEC (ADTRG). The hardware trigger is selected with the TRGSEL field in the
AFEC_MR. The selected hardware trigger is enabled with the TRGEN bit in the AFEC_MR.

The minimum time between two consecutive trigger events must be strictly greater than the duration time of the
longest conversion sequence according to configuration of registers AFEC_MR, AFEC_CHSR, AFEC_SEQR1,
AFEC_SEQR2.

If a hardware trigger is selected, the start of a conversion is triggered after a delay starting at each rising edge of
the selected signal. Due to asynchronous handling, the delay may vary in a range of 2 MCK clock periods to 1
AFEC clock period.

If one of the TIOA outputs is selected, the corresponding Timer Counter channel must be programmed in
Waveform Mode.

Only one start command is necessary to initiate a conversion sequence on all the channels. The AFEC hardware
logic automatically performs the conversions on the active channels, then waits for a new request. The Channel
Enable (AFEC_CHER) and Channel Disable (AFEC_CHDR) Registers permit the analog channels to be enabled
or disabled independently. 

If the AFEC is used with a  PDC, only the transfers of converted data from enabled channels are performed and
the resulting data buffers should be interpreted accordingly.

The AFEC Sleep Mode maximizes power saving by automatically deactivating the AFEC when it is not being used
for conversions. Sleep Mode is selected by setting the SLEEP bit in the AFEC_MR. 

The Sleep mode is automatically managed by a conversion sequencer, which can automatically process the
conversions of all channels at lowest power consumption.

trigger

start

delay