Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO Data Sheet
Product codes
ATSAM4E-XPRO
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
1444
The dynamic performances are the 12-bit mode values, reduced by 12 dB.
Low Voltage Supply
The ADC operates in 10-bit mode or 12-bit mode. Working at low voltage (VDDIN or/and V
ADVREF
) between 2 and
2.4V is subject to the following restrictions:
The field IBCTL must be 00 to reduce the biasing of the ADC under low voltage. See
In 10-bit mode, the ADC clock should not exceed 5 MHz (max signal bandwidth is 250 kHz).
In 12-bit mode, the ADC clock should not exceed 2 MHz (max signal bandwidth is 100 kHz).
47.7.5.3 ADC Channel Input Impedance
Figure 47-17.
Input Channel Model
where:
Z
IN
is input impedance in single-ended or differential mode
C
IN
= 1 to 8 pF +/-20% depending on the gain value and mode (SE or DIFF); temperature dependency is
negligible
R
ON
is typical 2 k
Ω
and 8 k
Ω
max (worst case process and high temperature)
R
ON
is negligible regarding the value of Z
IN
The following formula is used to calculate input impedance:
where:
f
S
is the sampling frequency of the ADC channel
Typ values are used to compute ADC input impedance Z
IN
Table 47-43.
Input Capacitance (C
IN
) Values
Gain Selection
Single-ended
Differential
0.5
N/A
2 pF
Cin
Zin
Ron
gnd
Single Ended model
Cin
Ron
Differential model
Zin
Ron
Z
IN
1
f
S
C
IN
×
--------------------
=