Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO Data Sheet

Product codes
ATSAM4E-XPRO
Page of 1506
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
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8.2
External Memories
The SAM4E device features one External Bus Interface to provide an interface to a wide range of external
memories and to any parallel peripheral.
8.3
Cortex-M Cache Controller (CMCC)
The SAM4E device features one cache memory and his controller which improve code execution when the code
runs out of Code section (memory from 0x0 to 0x2000_0000). 
The Cache controller handles both command instructions and data, it is an unified cache:
L1 data cache size set to 2 Kbytes
L1 cache line is 16 bytes
L1 cache integrates 32 bits bus master interface
Unified 4-way set associative cache architecture