Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO Data Sheet

321

SAM4E [DATASHEET]

Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_02-Jun-14

RSTC_MR

0x400E1808

Read/Write

This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register 
(SYSC_WPMR).



0: The detection of a low level on the pin NRST does not generate a user reset.

1: The detection of a low level on the pin NRST triggers a user reset.



0: USRTS bit in RSTC_SR at 1 has no effect on rstc_irq.

1: USRTS bit in RSTC_SR at 1 asserts rstc_irq if URSTEN = 0.



This field defines the external reset length. The external reset is asserted during a time of 2

(ERSTL+1)

 slow clock cycles. This 

allows assertion duration to be programmed between 60 µs and 2 seconds. Note that synchronization cycles must also be 
considered when calculating the actual reset length as previously described.



31

30

29

28

27

26

25

24

KEY

23

22

21

20

19

18

17

16

–

–

–

–

–

–

–

–

15

14

13

12

11

10

9

8

–

–

–

–

ERSTL

7

6

5

4

3

2

1

0

–

–

URSTIEN

–

–

–

URSTEN

0xA5

PASSWD

Writing any other value in this field aborts the write operation.

Always reads as 0.