Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO Data Sheet
Product codes
ATSAM4E-XPRO
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
466
26.
DMA Controller (DMAC)
26.1
Description
The DMA Controller (DMAC) is an AHB-central DMA controller core that transfers data from a source peripheral to
a destination peripheral over one or more AMBA buses. One channel is required for each source/destination pair.
In the most basic configuration, the DMAC has one master interface and one channel. The master interface reads
the data from a source and writes it to a destination. Two AMBA transfers are required for each DMAC data
transfer. This is also known as a dual-access transfer.
a destination peripheral over one or more AMBA buses. One channel is required for each source/destination pair.
In the most basic configuration, the DMAC has one master interface and one channel. The master interface reads
the data from a source and writes it to a destination. Two AMBA transfers are required for each DMAC data
transfer. This is also known as a dual-access transfer.
The DMAC is programmed via the APB interface.
26.2
Embedded Characteristics
1 AHB-Lite Master Interfaces
DMA Module Supports the Following Transfer Schemes: Peripheral-to-Memory, Memory-to-Peripheral,
Peripheral-to-Peripheral and Memory-to-Memory
Peripheral-to-Peripheral and Memory-to-Memory
Source and Destination Operate independently on BYTE (8-bit), HALF-WORD (16-bit) and WORD (32-bit)
Supports Hardware and Software Initiated Transfers
Supports Multiple Buffer Chaining Operations
Supports Incrementing/decrementing/fixed Addressing Mode Independently for Source and Destination
Programmable Arbitration Policy, Modified Round Robin and Fixed Priority are Available
Supports Specified Length and Unspecified Length AMBA AHB Burst Access to Maximize Data Bandwidth
AMBA APB Interface Used to Program the DMA Controller
4 DMA Channels 16 External Request Lines
Embedded FIFO
Channel Locking and Bus Locking Capability