Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO Data Sheet
Product codes
ATSAM4E-XPRO
525
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
28.
Static Memory Controller (SMC)
28.1
Description
The External Bus Interface is designed to ensure the successful data transfer between several external devices
and the Cortex-M4 based device. The External Bus Interface of the CM4P2 consists of a Static Memory Controller
(SMC).
and the Cortex-M4 based device. The External Bus Interface of the CM4P2 consists of a Static Memory Controller
(SMC).
This SMC is capable of handling several types of external memory and peripheral devices, such as SRAM,
PSRAM, PROM, EPROM, EEPROM, LCD Module, NOR Flash and NAND Flash.
PSRAM, PROM, EPROM, EEPROM, LCD Module, NOR Flash and NAND Flash.
The Static Memory Controller (SMC) generates the signals that control the access to the external memory devices
or peripheral devices. It has 4 Chip Selects, a 24-bit address bus, and an 8-bit data bus. Separate read and write
control signals allow for direct memory and peripheral interfacing. Read and write signal waveforms are fully
adjustable.
or peripheral devices. It has 4 Chip Selects, a 24-bit address bus, and an 8-bit data bus. Separate read and write
control signals allow for direct memory and peripheral interfacing. Read and write signal waveforms are fully
adjustable.
The SMC can manage wait requests from external devices to extend the current access. The SMC is provided with
an automatic slow clock mode. In slow clock mode, it switches from user-programmed waveforms to slow-rate
specific waveforms on read and write signals. The SMC supports asynchronous burst read in page mode access
for page size up to 32 bytes.
an automatic slow clock mode. In slow clock mode, it switches from user-programmed waveforms to slow-rate
specific waveforms on read and write signals. The SMC supports asynchronous burst read in page mode access
for page size up to 32 bytes.
The External Data Bus can be scrambled/unscrambled by means of user keys.
28.2
Embedded Characteristics
4 Chip Selects Available
16-Mbyte Address Space per Chip Select
8-bit Data Bus
Zero Wait State Scrambling/Unscrambling function with User Key
Word, Halfword, Byte Transfers
Programmable Setup, Pulse And Hold Time for Read Signals per Chip Select
Programmable Setup, Pulse And Hold Time for Write Signals per Chip Select
Programmable Data Float Time per Chip Select
External Data Bus Scrambling/Unscrambling Function
External Wait Request
Automatic Switch to Slow Clock Mode
Asynchronous Read in Page Mode Supported: Page Size Ranges from 4 to 32 Bytes
Write Protected Registers