Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO Data Sheet
Product codes
ATSAM4E-XPRO
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
584
29.6.1 Divider and Phase Lock Loop Programming
The divider can be set between 1 and 255 in steps of 1. When a divider field (DIV) is set to 0, the output of the
corresponding divider and the PLL output is a continuous signal at level 0. On reset, each DIV field is set to 0, thus
the corresponding PLL input clock is set to 0.
corresponding divider and the PLL output is a continuous signal at level 0. On reset, each DIV field is set to 0, thus
the corresponding PLL input clock is set to 0.
The PLL (PLLA) allows multiplication of the divider’s outputs. The PLL clock signal has a frequency that depends
on the respective source signal frequency and on the parameters DIV (DIVA) and MUL (MULA). The factor applied
to the source signal frequency is (MUL + 1)/DIV. When MUL is written to 0 or DIV=0,the PLL is disabled and its
power consumption is saved. Re-enabling the PLL can be performed by writing a value higher than 0 in the MUL
field and DIV higher than 0.
on the respective source signal frequency and on the parameters DIV (DIVA) and MUL (MULA). The factor applied
to the source signal frequency is (MUL + 1)/DIV. When MUL is written to 0 or DIV=0,the PLL is disabled and its
power consumption is saved. Re-enabling the PLL can be performed by writing a value higher than 0 in the MUL
field and DIV higher than 0.
Whenever the PLL is re-enabled or one of its parameters is changed, the LOCK (LOCKA) bit in PMC_SR is
automatically cleared. The values written in the PLLCOUNT field (PLLACOUNT) in CKGR_PLLR (CKGR_PLLAR)
are loaded in the PLL counter. The PLL counter then decrements at the speed of the slow clock until it reaches 0.
At this time, the LOCK bit is set in PMC_SR and can trigger an interrupt to the processor. The user has to load the
number of slow clock cycles required to cover the PLL transient time into the PLLCOUNT field.
automatically cleared. The values written in the PLLCOUNT field (PLLACOUNT) in CKGR_PLLR (CKGR_PLLAR)
are loaded in the PLL counter. The PLL counter then decrements at the speed of the slow clock until it reaches 0.
At this time, the LOCK bit is set in PMC_SR and can trigger an interrupt to the processor. The user has to load the
number of slow clock cycles required to cover the PLL transient time into the PLLCOUNT field.
The PLL clock can be divided by 2 by writing the PLLDIV2 (PLLADIV2) bit in PMC_MCKR.
To avoid programming the PLL with a multiplication factor that is too high, the user can saturate the multiplication
factor value sent to the PLL by setting the PLLA_MMAX field in PMC_PMMR.
factor value sent to the PLL by setting the PLLA_MMAX field in PMC_PMMR.
It is forbidden to change the 4/8/12 MHz fast RC oscillator, or the main selection in CKGR_MOR while the master
clock source is the PLL and the PLL reference clock is the fast RC oscillator.
clock source is the PLL and the PLL reference clock is the fast RC oscillator.
The user must:
Switch on the main RC oscillator by writing 1 in CSS field of PMC_MCKR.
Change the frequency (MOSCRCF) or oscillator selection (MOSCSEL) in CKGR_MOR.
Wait for MOSCRCS (if frequency changes) or MOSCSELS (if oscillator selection changes) in PMC_SR.
Disable and then enable the PLL (LOCK in PMC_IDR and PMC_IER).
Wait for LOCK flag in PMC_SR.
Switch back to PLL by writing the appropriate value to CSS field of PMC_MCKR.