Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO Data Sheet
Product codes
ATSAM4E-XPRO
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
716
34.5
Functional Description
The PIO Controller features up to 32 fully-programmable I/O lines. Most of the control logic associated to each I/O
is represented in
is represented in
. In this description each signal shown represents one of up to 32 possible indexes.
Figure 34-3.
I/O Line Control Logic
34.5.1 Pull-up and Pull-down Resistor Control
Each I/O line is designed with an embedded pull-up resistor and an embedded pull-down resistor. The pull-up
resistor can be enabled or disabled by writing to the Pull-up Enable register (PIO_PUER) or Pull-up Disable
register (PIO_PUDR), respectively. Writing to these registers results in setting or clearing the corresponding bit in
the Pull-up Status register (PIO_PUSR). Reading a one in PIO_PUSR means the pull-up is disabled and reading a
zero means the pull-up is enabled. The pull-down resistor can be enabled or disabled by writing the Pull-down
Enable register (PIO_PPDER) or the Pull-down Disable register (PIO_PPDDR), respectively. Writing in these
resistor can be enabled or disabled by writing to the Pull-up Enable register (PIO_PUER) or Pull-up Disable
register (PIO_PUDR), respectively. Writing to these registers results in setting or clearing the corresponding bit in
the Pull-up Status register (PIO_PUSR). Reading a one in PIO_PUSR means the pull-up is disabled and reading a
zero means the pull-up is enabled. The pull-down resistor can be enabled or disabled by writing the Pull-down
Enable register (PIO_PPDER) or the Pull-down Disable register (PIO_PPDDR), respectively. Writing in these
1
0
1
0
1
0
1
0
D
Q
D
Q
DFF
1
0
1
0
11
00
01
10
Programmable
Glitch
or
Debouncing
Filter
PIO_PDSR[0]
PIO_ISR[0]
PIO_IDR[0]
PIO_IMR[0]
PIO_IER[0]
PIO Interrupt
(Up to 32 possible inputs)
PIO_ISR[31]
PIO_IDR[31]
PIO_IMR[31]
PIO_IER[31]
Pad
PIO_PUDR[0]
PIO_PUSR[0]
PIO_PUER[0]
PIO_MDDR[0]
PIO_MDSR[0]
PIO_MDER[0]
PIO_CODR[0]
PIO_ODSR[0]
PIO_SODR[0]
PIO_PDR[0]
PIO_PSR[0]
PIO_PER[0]
PIO_ABCDSR1[0]
PIO_ODR[0]
PIO_OSR[0]
PIO_OER[0]
Peripheral Clock
Resynchronization
Stage
Peripheral A Input
Peripheral D Output Enable
Peripheral A Output Enable
EVENT
DETECTOR
DFF
PIO_IFDR[0]
PIO_IFSR[0]
PIO_IFER[0]
Peripheral Clock
Clock
Divider
PIO_IFSCSR[0]
PIO_IFSCER[0]
PIO_IFSCDR[0]
PIO_SCDR
Slow Clock
Peripheral B Output Enable
Peripheral C Output Enable
11
00
01
10
Peripheral D Output
Peripheral A Output
Peripheral B Output
Peripheral C Output
PIO_ABCDSR2[0]
Peripheral B Input
Peripheral C Input
Peripheral D Input
PIO_PPDDR[0]
PIO_PPDSR[0]
PIO_PPDER[0]
VDD
GND
Integrated
Pull-Down
Pull-Down
Resistor
Integrated
Pull-Up
Resistor
div_slclk