Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO Data Sheet
Product codes
ATSAM4E-XPRO
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
826
36.7.3 Master Mode
36.7.3.1 Definition
The Master is the device that starts a transfer, generates a clock and stops it.
36.7.3.2 Application Block Diagram
Figure 36-5.
Master Mode Typical Application Block Diagram
36.7.3.3 Programming Master Mode
The following registers have to be programmed before entering Master mode:
1.
DADR (+ IADRSZ + IADR if a 10-bit device is addressed): The device address is used to access slave devices in
read or write mode.
read or write mode.
2.
CKDIV + CHDIV + CLDIV: Clock Waveform.
3.
SVDIS: Disable the slave mode.
4.
MSEN: Enable the master mode.
Note:
If the TWI is already in Master mode, the device address (DADR) can be configured without disabling the Master
mode.
mode.
36.7.3.4 Master Transmitter Mode
After the master initiates a Start condition when writing into the Transmit Holding Register (TWI_THR) it sends a 7-
bit slave address, configured in the Master Mode Register (DADR in TWI_MMR), to notify the slave device. The bit
following the slave address indicates the transfer direction—0 in this case (MREAD = 0 in TWI_MMR).
bit slave address, configured in the Master Mode Register (DADR in TWI_MMR), to notify the slave device. The bit
following the slave address indicates the transfer direction—0 in this case (MREAD = 0 in TWI_MMR).
The TWI transfers require the slave to acknowledge each received byte. During the acknowledge clock pulse (9th
pulse), the master releases the data line (HIGH), enabling the slave to pull it down in order to generate the
acknowledge. The master polls the data line during this clock pulse and sets the Not Acknowledge bit (NACK) in
the Status Register (TWI_SR) if the slave does not acknowledge the byte. As with the other status bits, an interrupt
can be generated if enabled in the Interrupt Enable Register (TWI_IER). If the slave acknowledges the byte, the
data written in the TWI_THR, is then shifted in the internal shifter and transferred. When an acknowledge is
detected, the TXRDY bit is set until a new write in the TWI_THR.
pulse), the master releases the data line (HIGH), enabling the slave to pull it down in order to generate the
acknowledge. The master polls the data line during this clock pulse and sets the Not Acknowledge bit (NACK) in
the Status Register (TWI_SR) if the slave does not acknowledge the byte. As with the other status bits, an interrupt
can be generated if enabled in the Interrupt Enable Register (TWI_IER). If the slave acknowledges the byte, the
data written in the TWI_THR, is then shifted in the internal shifter and transferred. When an acknowledge is
detected, the TXRDY bit is set until a new write in the TWI_THR.
TXRDY is used as Transmit Ready for the PDC transmit channel.
While no new data is written in the TWI_THR, the Serial Clock Line is tied low. When new data is written in the
TWI_THR, the SCL is released and the data is sent. Setting the STOP bit in TWI_CR generates a STOP condition.
TWI_THR, the SCL is released and the data is sent. Setting the STOP bit in TWI_CR generates a STOP condition.
After a Master Write transfer, the Serial Clock line is stretched (tied low) while no new data is written in the
TWI_THR or until a STOP command is performed.
TWI_THR or until a STOP command is performed.
Host with
TWI
Interface
TWD
TWCK
Atmel TWI
Serial EEPROM
I²C RTC
I²C LCD
Controller
Slave 1
Slave 2
Slave 3
V
DD
I²C Temp.
Sensor
Slave 4
Rp: Pull-up value as given by the I²C Standard
Rp
Rp