Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO Data Sheet

Product codes
ATSAM4E-XPRO
Page of 1506
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
856
36.8.6 TWI Status Register
Name: TWI_SR
Address:
0x400A8020 (0), 0x400AC020 (1)
Access: Read-only
Reset: 
0x0000F009
TXCOMP: Transmission Completed (automatically set / reset)
TXCOMP used in Master mode: 
0: During the length of the current frame.
1: When both holding register and internal shifter are empty and STOP condition has been sent.
TXCOMP behavior in Master mode can be seen in 
 and in 
TXCOMP used in Slave mode:
0: As soon as a Start is detected.
1: After a Stop or a Repeated Start + an address different from SADR is detected.
TXCOMP behavior in Slave mode can be seen in 
 an
RXRDY: Receive Holding Register Ready (automatically set / reset)
0: No character has been received since the last TWI_RHR read operation.
1: A byte has been received in the TWI_RHR since the last read.
RXRDY behavior in Master mode can be seen in 
.
RXRDY behavior in Slave mode can be seen in 
 an
TXRDY: Transmit Holding Register Ready (automatically set / reset)
TXRDY used in Master mode:
0: The transmit holding register has not been transferred into internal shifter. Set to 0 when writing into TWI_THR.
1: As soon as a data byte is transferred from TWI_THR to internal shifter or if a NACK error is detected, TXRDY is set at 
the same time as TXCOMP and NACK. TXRDY is also set when MSEN is set (enable TWI).
TXRDY behavior in Master mode can be seen in 
.
TXRDY used in Slave mode:
0: As soon as data is written in the TWI_THR, until this data has been transmitted and acknowledged (ACK or NACK).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
TXBUFE
RXBUFF
ENDTX
ENDRX
EOSACC
SCLWS
ARBLST
NACK
7
6
5
4
3
2
1
0
OVRE
GACC
SVACC
SVREAD
TXRDY
RXRDY
TXCOMP