Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet
Product codes
AT91SAM9N12-EK
469
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
32.5.4.2 Programming DMAC for Multiple Buffer Transfers
Notes: 1. USR means that the register field is manually programmed by the user.
2. CONT means that address are contiguous.
3. REP means that the register field is updated with its previous value. If the transfer is the first one, then the user must
manually program the value.
4. Channel stalled is true if the relevant BTC interrupt is not masked.
5. LLI means that the register field is updated with the content of the linked list item.
Replay Mode of Channel Registers
During automatic replay mode, the channel registers are reloaded with their initial values at the completion of each buffer
and the new values used for the new buffer. Depending on the row number in
and the new values used for the new buffer. Depending on the row number in
, some or all of the
DMAC_SADDRx, DMAC_DADDRx, DMAC_CTRLAx and DMAC_CTRLBx channel registers are reloaded from their
initial value at the start of a buffer transfer.
initial value at the start of a buffer transfer.
Contiguous Address Between Buffers
In this case, the address between successive buffers is selected to be a continuation from the end of the previous buffer.
E n a b l i n g t h e s o u r c e o r d e s t i n a t i o n a d d r e s s t o b e c o n t i g u o u s b e t w e e n b u f f e r s i s a f u n c t i o n o f
DMAC_CTRLAx.SRC_DSCR, DMAC_CFGx.DST_REP, DMAC_CFGx.SRC_REP and DMAC_CTRLAx.DST_DSCR
registers.
E n a b l i n g t h e s o u r c e o r d e s t i n a t i o n a d d r e s s t o b e c o n t i g u o u s b e t w e e n b u f f e r s i s a f u n c t i o n o f
DMAC_CTRLAx.SRC_DSCR, DMAC_CFGx.DST_REP, DMAC_CFGx.SRC_REP and DMAC_CTRLAx.DST_DSCR
registers.
Table 32-2. Multiple Buffers Transfer Management Table
Transfer Type
AUTO
SRC_REP
DST_REP
SRC_DSCR
DST_DSCR
BTSIZE
DSCR
SADDR
DADDR
Other Fields
1) Single Buffer or Last
buffer of a multiple buffer
transfer
0
–
–
–
–
USR
0
USR
USR
USR
2) Multi Buffer transfer with
contiguous DADDR
0
–
0
0
1
LLI
USR
LLI
CONT
LLI
3) Multi Buffer transfer with
contiguous SADDR
0
0
–
1
0
LLI
USR
CONT
LLI
LLI
4) Multi Buffer transfer with
LLI support
0
–
–
0
0
LLI
USR
LLI
LLI
LLI
5) Multi Buffer transfer with
DADDR reloaded
0
–
1
0
1
LLI
USR
LLI
REP
LLI
6) Multi Buffer transfer with
SADDR reloaded
0
1
–
1
0
LLI
USR
REP
LLI
LLI
7) Multi Buffer transfer
with BTSIZE reloaded and
contiguous DADDR
1
–
0
0
1
REP
USR
LLI
CONT
LLI
8) Multi Buffer transfer with
BTSIZE reloaded and
contiguous SADDR
1
0
–
1
0
REP
USR
CONT
LLI
LLI
9) Automatic mode channel
is stalling
BTsize is reloaded
1
0
0
1
1
REP
USR
CONT
CONT
REP
10) Automatic mode
BTSIZE, SADDR and
DADDR reloaded
1
1
1
1
1
REP
USR
REP
REP
REP
11) Automatic mode
BTSIZE, SADDR reloaded
and DADDR contiguous
1
1
0
1
1
REP
USR
REP
CONT
REP