Atmel Evaluation Kit AT91SAM9X25-EK AT91SAM9X25-EK Data Sheet
Product codes
AT91SAM9X25-EK
453
SAM9X25 [DATASHEET]
11054E–ATARM–10-Mar-2014
Table 30-4. Linear Mapping for SDRAM Configuration: 16K Rows, 512/1024/2048 Columns
CPU Address Line
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bk[1:0]
Row[13:0]
Column[8:0]
M0
Bk[1:0]
Row[13:0]
Column[9:0]
M0
Bk[1:0]
Row[13:0]
Column[10:0]
M0
Table 30-5. Interleaved Mapping for SDRAM Configuration, 2K Rows, 512/1024/2048/4096 Columns
CPU Address Line
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Row[10:0]
Bk[1:0]
Column[8:0]
M0
Row[10:0]
Bk[1:0]
Column[9:0]
M0
Row[10:0]
Bk[1:0]
Column[10:0]
M0
Row[10:0]
Bk[1:0]
Column[11:0]
M0
Table 30-6. Interleaved Mapping for SDRAM Configuration: 4K Rows, 512/1024/2048/4096 Columns
CPU Address Line
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Row[11:0]
Bk[1:0]
Column[8:0]
M0
Row[11:0]
Bk[1:0]
Column[9:0]
M0
Row[11:0]
Bk[1:0]
Column[10:0]
M0
Row[11:0]
Bk[1:0]
Column[11:0]
M0
Table 30-7. Interleaved Mapping for SDRAM Configuration: 8K Rows, 512/1024/2048/4096 Columns
CPU Address Line
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Row[12:0]
Bk[1:0]
Column[8:0]
M0
Row[12:0]
Bk[1:0]
Column[9:0]
M0
Row[12:0]
Bk[1:0]
Column[10:0]
M0
Row[12:0]
Bk[1:0]
Column[11:0]
M0