Atmel Evaluation Kit AT91SAM9X25-EK AT91SAM9X25-EK Data Sheet
Product codes
AT91SAM9X25-EK
663
SAM9X25 [DATASHEET]
11054E–ATARM–10-Mar-2014
35.6.2 Power Management
The SPI may be clocked through the Power Management Controller (PMC), thus the programmer must first configure the
PMC to enable the SPI clock.
PMC to enable the SPI clock.
35.6.3 Interrupt
The SPI interface has an interrupt line connected to the Interrupt Controller. Handling the SPI interrupt requires
programming the interrupt controller before configuring the SPI.
programming the interrupt controller before configuring the SPI.
35.6.4 Direct Memory Access Controller (DMAC)
The SPI interface can be used in conjunction with the DMAC in order to reduce processor overhead. For a full description
of the DMAC, refer to the corresponding section in the full datasheet.
of the DMAC, refer to the corresponding section in the full datasheet.
35.7 Functional Description
35.7.1 Modes of Operation
The SPI operates in Master Mode or in Slave Mode.
Operation in Master Mode is programmed by writing at 1 the MSTR bit in the Mode Register. The pins NPCS0 to NPCS3
are all configured as outputs, the SPCK pin is driven, the MISO line is wired on the receiver input and the MOSI line
driven as an output by the transmitter.
are all configured as outputs, the SPCK pin is driven, the MISO line is wired on the receiver input and the MOSI line
driven as an output by the transmitter.
If the MSTR bit is written at 0, the SPI operates in Slave Mode. The MISO line is driven by the transmitter output, the
MOSI line is wired on the receiver input, the SPCK pin is driven by the transmitter to synchronize the receiver. The
NPCS0 pin becomes an input, and is used as a Slave Select signal (NSS). The pins NPCS1 to NPCS3 are not driven
and can be used for other purposes.
MOSI line is wired on the receiver input, the SPCK pin is driven by the transmitter to synchronize the receiver. The
NPCS0 pin becomes an input, and is used as a Slave Select signal (NSS). The pins NPCS1 to NPCS3 are not driven
and can be used for other purposes.
The data transfers are identically programmable for both modes of operations. The baud rate generator is activated only
in Master Mode.
in Master Mode.
SPI0
SPI0_NPCS0
PA14
A
SPI0
SPI0_NPCS1
PA7
B
SPI0
SPI0_NPCS2
PA1
B
SPI0
SPI0_NPCS3
PB3
B
SPI0
SPI0_SPCK
PA13
A
SPI1
SPI1_MISO
PA21
B
SPI1
SPI1_MOSI
PA22
B
SPI1
SPI1_NPCS0
PA8
B
SPI1
SPI1_NPCS1
PA0
B
SPI1
SPI1_NPCS2
PA31
B
SPI1
SPI1_NPCS3
PA30
B
SPI1
SPI1_SPCK
PA23
B
Table 35-2. I/O Lines
Table 35-3. Peripheral IDs
Instance
ID
SPI0
13
SPI1
14