Atmel SAM4S-EK2 Atmel ATSAM4S-EK2 ATSAM4S-EK2 Data Sheet

 392

SAM4S [DATASHEET]

11100E–ATARM–24-Jul-13

Note: When NAND Flash logic is activated, (SMCNFCSx=1), NWE pin cannot be used i PIO Mode but only in peripheral
mode (NWE function). If NWE function is not used for other external memories (SRAM, LCD), it must be configured in
one of the following modes.



PIO Input with pull-up enabled (default state after reset)



PIO Output set at level 1

The address latch enable and command latch enable signals on the NAND Flash device are driven by address bits A22
and A21of the address bus. Any bit of the address bus can also be used for this purpose. The command, address or data
words on the data bus of the NAND Flash device use their own addresses within the NCSx address space (configured by
CCFG_SMCNFCS Register on the Bus Matrix User Interface). The chip enable (CE) signal of the device and the
ready/busy (R/B) signals are connected to PIO lines. The CE signal then remains asserted even when NCS3 is not
selected, preventing the device from returning to standby mode. The NANDCS output signal should be used in
accordance with the external NAND Flash device type. 

Two types of CE behavior exist depending on the NAND flash device:



Standard NAND Flash devices require that the CE pin remains asserted Low continuously during the read busy 
period to prevent the device from returning to standby mode. Since the Static Memory Controller (SMC) asserts 
the NCSx signal High, it is necessary to connect the CE pin of the NAND Flash device to a GPIO line, in order to 
hold it low during the busy period preceding data read out.



This restriction has been removed for “CE don’t care” NAND Flash devices. The NCSx signal can be directly 
connected to the CE pin of the NAND Flash device.

SMC

NRD

NWE

NANDOE

NANDWE

NAND Flash Logic

NCSx (activated if SMC_NFCSx=1) *

NANDWE

NANDOE

* in CCFG_SMCNFCS Matrix register