Atmel SAM4S-EK2 Atmel ATSAM4S-EK2 ATSAM4S-EK2 Data Sheet
Product codes
ATSAM4S-EK2
461
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
28.2.8 Peripheral Clock Controller
The Power Management Controller controls the clocks of each embedded peripheral by means of the
Peripheral Clock Controller. The user can individually enable and disable the Clock on the
peripherals.
Peripheral Clock Controller. The user can individually enable and disable the Clock on the
peripherals.
The user can also enable and disable these clocks by writing Peripheral Clock Enable 0
(PMC_PCER0), Peripheral Clock Disable 0 (PMC_PCDR0), Peripheral Clock Enable 1
(PMC_PCER1) and Peripheral Clock Disable 1 (PMC_PCDR1) registers. The status of the peripheral
clock activity can be read in the Peripheral Clock Status Register (PMC_PCSR0) and Peripheral
Clock Status Register (PMC_PCSR1).
(PMC_PCER0), Peripheral Clock Disable 0 (PMC_PCDR0), Peripheral Clock Enable 1
(PMC_PCER1) and Peripheral Clock Disable 1 (PMC_PCDR1) registers. The status of the peripheral
clock activity can be read in the Peripheral Clock Status Register (PMC_PCSR0) and Peripheral
Clock Status Register (PMC_PCSR1).
When a peripheral clock is disabled, the clock is immediately stopped. The peripheral clocks are
automatically disabled after a reset.
automatically disabled after a reset.
In order to stop a peripheral, it is recommended that the system software wait until the peripheral has
executed its last programmed operation before disabling the clock. This is to avoid data corruption or
erroneous behavior of the system.
executed its last programmed operation before disabling the clock. This is to avoid data corruption or
erroneous behavior of the system.
The bit number within the Peripheral Clock Control registers (PMC_PCER0-1, PMC_PCDR0-1, and
PMC_PCSR0-1) is the Peripheral Identifier defined at the product level. The bit number corresponds
to the interrupt source number assigned to the peripheral.
PMC_PCSR0-1) is the Peripheral Identifier defined at the product level. The bit number corresponds
to the interrupt source number assigned to the peripheral.
28.2.9 Free Running Processor Clock
The Free Running Processor Clock (FCLK) used for sampling interrupts and clocking debug blocks
ensures that interrupts can be sampled, and sleep events can be traced, while the processor is
sleeping. It is connected to Master Clock (MCK).
ensures that interrupts can be sampled, and sleep events can be traced, while the processor is
sleeping. It is connected to Master Clock (MCK).
28.2.10 Programmable Clock Output Controller
The PMC controls 3 signals to be output on external pins, PCKx. Each signal can be independently
programmed via the Programmable Clock Registers (PMC_PCKx).
programmed via the Programmable Clock Registers (PMC_PCKx).
PCKx can be independently selected between the Slow Clock (SLCK), the Main Clock (MAINCK), the
PLLA Clock (PLLACK), the PLLB Clock (PLLBCK),and the Master Clock (MCK) by writing the CSS
field in PMC_PCKx. Each output signal can also be divided by a power of 2 between 1 and 64 by
writing the PRES (Prescaler) field in PMC_PCKx.
PLLA Clock (PLLACK), the PLLB Clock (PLLBCK),and the Master Clock (MCK) by writing the CSS
field in PMC_PCKx. Each output signal can also be divided by a power of 2 between 1 and 64 by
writing the PRES (Prescaler) field in PMC_PCKx.
Each output signal can be enabled and disabled by writing 1 in the corresponding bit, PCKx of
PMC_SCER and PMC_SCDR, respectively. Status of the active programmable output clocks are
given in the PCKx bits of PMC_SCSR (System Clock Status Register).
PMC_SCER and PMC_SCDR, respectively. Status of the active programmable output clocks are
given in the PCKx bits of PMC_SCSR (System Clock Status Register).
Moreover, like the PCK, a status bit in PMC_SR indicates that the Programmable Clock is actually
what has been programmed in the Programmable Clock registers.
what has been programmed in the Programmable Clock registers.
As the Programmable Clock Controller does not manage with glitch prevention when switching
clocks, it is strongly recommended to disable the Programmable Clock before any configuration
change and to re-enable it after the change is actually performed.
clocks, it is strongly recommended to disable the Programmable Clock before any configuration
change and to re-enable it after the change is actually performed.
28.2.11 Fast Start-up
The device allows the processor to restart in less than 10 microseconds while the device is in Wait
Mode.
Mode.
The system enters Wait Mode either by writing the WAITMODE bit at 1 in the PMC Clock Generator
Main Oscillator Register (CKGR_MOR), or by executing the WaitForEvent (WFE) instruction of the
processor while the LPM bit is at 1 in the PMC Fast Start-up Mode Register (PMC_FSMR). Waiting
for the MOSCRCEN bit to be cleared is strongly recommended to ensure that the core will not
execute undesired instructions.
Main Oscillator Register (CKGR_MOR), or by executing the WaitForEvent (WFE) instruction of the
processor while the LPM bit is at 1 in the PMC Fast Start-up Mode Register (PMC_FSMR). Waiting
for the MOSCRCEN bit to be cleared is strongly recommended to ensure that the core will not
execute undesired instructions.