Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Data Sheet
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Product codes
AT91SAM9M10-G45-EK
1016
SAM9M10 [DATASHEET]
6355F–ATARM–12-Mar-13
43.8
AC97 Controller (AC97C) User Interface
Table 43-6.
Register Mapping
Offset
Register
Name
Access
Reset
0x0-0x4
Reserved
–
–
–
0x8
Mode Register
AC97C_MR
Read-write
0x0
0xC
Reserved
–
–
–
0x10
Input Channel Assignment Register
AC97C_ICA
Read-write
0x0
0x14
Output Channel Assignment Register
AC97C_OCA
Read-write
0x0
0x18-0x1C
Reserved
–
–
–
0x20
Channel A Receive Holding Register
AC97C_CARHR
Read
0x0
0x24
Channel A Transmit Holding Register
AC97C_CATHR
Write
–
0x28
Channel A Status Register
AC97C_CASR
Read
0x0
0x2C
Channel A Mode Register
AC97C_CAMR
Read-write
0x0
0x30
Channel B Receive Holding Register
AC97C_CBRHR
Read
0x0
0x34
Channel B Transmit Holding Register
AC97C_CBTHR
Write
–
0x38
Channel B Status Register
AC97C_CBSR
Read
0x0
0x3C
Channel B Mode Register
AC97C_CBMR
Read-write
0x0
0x40
Codec Channel Receive Holding Register
AC97C_CORHR
Read
0x0
0x44
Codec Channel Transmit Holding Register
AC97C_COTHR
Write
–
0x48
Codec Status Register
AC97C_COSR
Read
0x0
0x4C
Codec Mode Register
AC97C_COMR
Read-write
0x0
0x50
Status Register
AC97C_SR
Read
0x0
0x54
Interrupt Enable Register
AC97C_IER
Write
–
0x58
Interrupt Disable Register
AC97C_IDR
Write
–
0x5C
Interrupt Mask Register
AC97C_IMR
Read
0x0
0x60-0xFB
Reserved
–
–
–
0x100-0x124
Reserved for Peripheral DMA Controller (PDC)
registers related to channel transfers
registers related to channel transfers
–
–
–