Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Data Sheet
Product codes
AT91SAM9M10-G45-EK
1051
SAM9M10 [DATASHEET]
6355F–ATARM–12-Mar-13
• The input interface connects the datapath with the DMA controller. It is a dual FIFO interface with a data bus
and two push lines that are used by the DMA controller to fill the FIFOs.
• The output interface is a 24-bit data bus. The configuration of this interface depends on the type of LCD used
(TFT or STN, Single or Dual Scan, 4-bit, 8-bit, 16-bit or 24-bit interface).
• The configuration interface connects the datapath with the configuration block. It is used to select between the
different datapath configurations.
• The control interface connects the datapath with the timing generation block. The main control signal is the
data-request signal, used by the timing generation module to request new data from the datapath.
The datapath can be characterized by two parameters: initial_latency and cycles_per_data. The parameter
initial_latency is defined as the number of LCDC Core Clock cycles until the first data is available at the output of
the datapath. The parameter cycles_per_data is the minimum number of LCDC Core clock cycles between two
consecutive data at the output interface.
initial_latency is defined as the number of LCDC Core Clock cycles until the first data is available at the output of
the datapath. The parameter cycles_per_data is the minimum number of LCDC Core clock cycles between two
consecutive data at the output interface.
These parameters are different for the different configurations of the LCD Controller and are shown in
.
45.6.2.3
FIFO
The FIFO block buffers the input data read by the DMA module. It contains two input FIFOs to be used in Dual
Scan configuration that are configured as a single FIFO when used in single scan configuration.
Scan configuration that are configured as a single FIFO when used in single scan configuration.
The size of the FIFOs allows a wide range of architectures to be supported.
The upper threshold of the FIFOs can be configured in the FIFOTH field of the LCDFIFO register. The LCDC core
will request a DMA transfer when the number of words in each FIFO is less than FIFOTH words. To avoid overwrit-
ing in the FIFO and to maximize the FIFO utilization, the FIFOTH should be programmed with:
will request a DMA transfer when the number of words in each FIFO is less than FIFOTH words. To avoid overwrit-
ing in the FIFO and to maximize the FIFO utilization, the FIFOTH should be programmed with:
FIFOTH (in Words) = 512 - (2 x DMA_BURST_LENGTH + 3)
where:
• 512 is the effective size of the FIFO in Words. It is the total FIFO memory size in single scan mode and half that
size in dual scan mode.
• DMA_burst_length is the burst length of the transfers made by the DMA in Words.
45.6.2.4
Serializer
This block serializes the data read from memory. It reads words from the FIFO and outputs pixels (1 bit, 2 bits, 4
bits, 8 bits, 16 bits or 24 bits wide) depending on the format specified in the PIXELSIZE field of the LCDCON2 reg-
bits, 8 bits, 16 bits or 24 bits wide) depending on the format specified in the PIXELSIZE field of the LCDCON2 reg-
Table 45-4.
Datapath Parameters
Configuration
initial_latency
cycles_per_data
DISTYPE
SCAN
IFWIDTH
TFT
9
1
STN Mono
Single
4
13
4
STN Mono
Single
8
17
8
STN Mono
Dual
8
17
8
STN Mono
Dual
16
25
16
STN Color
Single
4
11
2
STN Color
Single
8
12
3
STN Color
Dual
8
14
4
STN Color
Dual
16
15
6