Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Data Sheet

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SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

At the end of the current access, if no other request is pending, the slave remains connected to its associated
default master. A slave can be associated with three kinds of default masters: no default master, last access mas-
ter and fixed default master.

To change from one kind of default master to another, the Bus Matrix user interface provides the Slave Configura-
tion Registers, one for each slave, that set a default master for each slave. The Slave Configuration Register
contains two fields: DEFMSTR_TYPE and FIXED_DEFMSTR. The 2-bit DEFMSTR_TYPE field selects the default
master type (no default, last access master, fixed default master), whereas the 4-bit FIXED_DEFMSTR field
selects a fixed default master provided that DEFMSTR_TYPE is set to fixed default master. Please refer to 

.

After the end of the current access, if no other request is pending, the slave is disconnected from all masters. No
Default Master suits low-power mode.

This configuration incurs one latency clock cycle for the first access of a burst after bus Idle. Arbitration without
default master may be used for masters that perform significant bursts or several transfers with no Idle in between,
or if the slave bus bandwidth is widely used by one or more masters.

This configuration provides no benefit on access latency or bandwidth when reaching maximum slave bus through-
put whatever is the number of requesting masters.

After the end of the current access, if no other request is pending, the slave remains connected to the last master
that performed an access request.

This allows the Bus Matrix to remove the one latency cycle for the last master that accessed the slave. Other non
privileged masters still get one latency clock cycle if they want to access the same slave. This technique is useful
for masters that mainly perform single accesses or short bursts with some Idle cycles in between.

This configuration provides no benefit on access latency or bandwidth when reaching maximum slave bus through-
put whatever is the number of requesting masters.

After the end of the current access, if no other request is pending, the slave connects to its fixed default master.
Unlike last access master, the fixed master does not change unless the user modifies it by a software action (field
FIXED_DEFMSTR of the related MATRIX_SCFG).

This allows the Bus Matrix arbiters to remove the one latency clock cycle for the fixed default master of the slave.
Every request attempted by this fixed default master will not cause any arbitration latency whereas other non privi-
leged masters will still get one latency cycle. This technique is useful for a master that mainly perform single
accesses or short bursts with some Idle cycles in between.

This configuration provides no benefit on access latency or bandwidth when reaching maximum slave bus through-
put whatever is the number of requesting masters.

The Bus Matrix provides an arbitration mechanism that reduces latency when conflict cases occur, i.e. when two or
more masters try to access the same slave at the same time. One arbiter per AHB slave is provided, thus arbitrat-
ing each slave differently.

The Bus Matrix provides the user with the possibility of choosing between 2 arbitration types or mixing them for
each slave: