Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Data Sheet
Product codes
AT91SAM9M10-G45-EK
181
SAM9M10 [DATASHEET]
6355F–ATARM–12-Mar-13
21. Static Memory Controller (SMC)
21.1
Description
The Static Memory Controller (SMC) generates the signals that control the access to the external memory devices
or peripheral devices. It has 6 Chip Selects and a 26-bit address bus. The 32-bit data bus can be configured to
interface with 8-, 16-, or 32-bit external devices. Separate read and write control signals allow for direct memory
and peripheral interfacing. Read and write signal waveforms are fully parametrizable.
or peripheral devices. It has 6 Chip Selects and a 26-bit address bus. The 32-bit data bus can be configured to
interface with 8-, 16-, or 32-bit external devices. Separate read and write control signals allow for direct memory
and peripheral interfacing. Read and write signal waveforms are fully parametrizable.
The SMC can manage wait requests from external devices to extend the current access. The SMC is provided with
an automatic slow clock mode. In slow clock mode, it switches from user-programmed waveforms to slow-rate spe-
cific waveforms on read and write signals. The SMC supports asynchronous burst read in page mode access for
page size up to 32 bytes.
an automatic slow clock mode. In slow clock mode, it switches from user-programmed waveforms to slow-rate spe-
cific waveforms on read and write signals. The SMC supports asynchronous burst read in page mode access for
page size up to 32 bytes.
21.2
I/O Lines Description
21.3
Multiplexed Signals
Table 21-1.
I/O Line Description
Name
Description
Type
Active Level
NCS[7:0]
Static Memory Controller Chip Select Lines
Output
Low
NRD
Read Signal
Output
Low
NWR0/NWE
Write 0/Write Enable Signal
Output
Low
A0/NBS0
Address Bit 0/Byte 0 Select Signal
Output
Low
NWR1/NBS1
Write 1/Byte 1 Select Signal
Output
Low
A1/NWR2/NBS2
Address Bit 1/Write 2/Byte 2 Select Signal
Output
Low
NWR3/NBS3
Write 3/Byte 3 Select Signal
Output
Low
A[25:2]
Address Bus
Output
D[31:0] Data
Bus
I/O
NWAIT
External Wait Signal
Input
Low
Table 21-2.
Static Memory Controller (SMC) Multiplexed Signals
Multiplexed Signals
Related Function
NWR0
NWE
A0
NBS0
8-bit or 16-/32-bit data bus, see
NWR1
NBS1
Byte-write or byte-select access see
A1
NWR2
NBS2
8-/16-bit or 32-bit data bus, see
NWR3
NBS3
Byte-write or byte-select access see