Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Data Sheet

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SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

When switching from slow clock mode to the normal mode, the current slow clock mode transfer is completed at
high clock rate, with the set of slow clock mode parameters.See 

. The external device

may not be fast enough to support such timings. 

Clock Rate Transition Occurs while the SMC is Performing a Write Operation 

A

[25:2]

NCS

1

MCK

NWE

1

1

NWE_CYCLE = 3

SLOW CLOCK MODE WRITE

Slow Clock Mode

internal signal from PMC

1

1

1

2

3

2

NWE_CYCLE = 7

NORMAL MODE WRITE

Slow clock mode transition is detected: 

Reload Configuration Wait State

This write cycle finishes with the slow clock mode set

of parameters  after the clock rate transition

SLOW CLOCK MODE WRITE

NBS0, NBS1,
NBS2, NBS3,
A0,A1