Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Data Sheet

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SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

Deep Power-down Mode Entry

The reset mode is a feature of the DDR2-SDRAM. This mode is activated by setting the low-power command bits
(LPCB) to 11 and the clock frozen command bit (CLK_FR) to 1.

When this mode is enabled, the DDRSDRC leaves normal mode (mode == 000) and the controller is frozen.
Before enabling this mode, the end user must assume there is not an access in progress. 

To exit reset mode, the low-power command bits (LPCB) must be set to “00”, clock frozen command bit (CLK_FR)
set to 0 and an initialization sequence must be generated by software. See 

NOP READ

BST

NOP

PRCHG

NOP

DEEPOWER

NOP

0

Trp

Enter Deep
Power-down
Mode

SDCLK

A[12:0]

COMMAND

CKE

BA[1:0]

DQS[1:0]

Da

Db

D[15:0]

3

DM[1:0]