Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Data Sheet

 389

SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

In Master Mode, the SPI Interface uses a modulus counter to derive the SPCK baud rate from the Master Clock MCK. The
Baud rate is selected by writing a value from 1 to 255 in the SCBR field. The following equations determine the SPCK baud
rate:

Programming the SCBR field at 0 is forbidden. Triggering a transfer while SCBR is at 0 can lead to unpredictable results. 

At reset, SCBR is 0 and the user has to program it at a valid value before performing the first transfer.

This field defines the delay from NPCS valid to the first valid SPCK transition. 

When DLYBS equals zero, the NPCS valid to SPCK transition is 1/2 the SPCK clock period.

Otherwise, the following equations determine the delay:

This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select.
The delay is always inserted after each transfer and before removing the chip select if needed.

When DLYBCT equals zero, no delay between consecutive transfers is inserted and the clock keeps its duty cycle over the
character transfers.

Otherwise, the following equation determines the delay:

1001

Reserved

1010

Reserved

1011

Reserved

1100

Reserved

1101

Reserved

1110

Reserved

1111

Reserved

 SPCK Baudrate

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=

Delay Before SPCK

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=

Delay Between Consecutive Transfers

32

×

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=